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180 lines
4.9 KiB
180 lines
4.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* linux/arch/arm/include/asm/pmu.h |
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* |
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* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles |
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*/ |
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#ifndef __ARM_PMU_H__ |
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#define __ARM_PMU_H__ |
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#include <linux/interrupt.h> |
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#include <linux/perf_event.h> |
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#include <linux/platform_device.h> |
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#include <linux/sysfs.h> |
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#include <asm/cputype.h> |
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#ifdef CONFIG_ARM_PMU |
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/* |
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* The ARMv7 CPU PMU supports up to 32 event counters. |
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*/ |
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#define ARMPMU_MAX_HWEVENTS 32 |
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/* |
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* ARM PMU hw_event flags |
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*/ |
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/* Event uses a 64bit counter */ |
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#define ARMPMU_EVT_64BIT 1 |
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#define HW_OP_UNSUPPORTED 0xFFFF |
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#define C(_x) PERF_COUNT_HW_CACHE_##_x |
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#define CACHE_OP_UNSUPPORTED 0xFFFF |
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#define PERF_MAP_ALL_UNSUPPORTED \ |
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[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED |
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#define PERF_CACHE_MAP_ALL_UNSUPPORTED \ |
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[0 ... C(MAX) - 1] = { \ |
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[0 ... C(OP_MAX) - 1] = { \ |
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[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \ |
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}, \ |
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} |
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/* The events for a given PMU register set. */ |
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struct pmu_hw_events { |
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/* |
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* The events that are active on the PMU for the given index. |
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*/ |
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struct perf_event *events[ARMPMU_MAX_HWEVENTS]; |
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/* |
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* A 1 bit for an index indicates that the counter is being used for |
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* an event. A 0 means that the counter can be used. |
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*/ |
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DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS); |
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/* |
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* Hardware lock to serialize accesses to PMU registers. Needed for the |
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* read/modify/write sequences. |
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*/ |
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raw_spinlock_t pmu_lock; |
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/* |
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* When using percpu IRQs, we need a percpu dev_id. Place it here as we |
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* already have to allocate this struct per cpu. |
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*/ |
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struct arm_pmu *percpu_pmu; |
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int irq; |
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}; |
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enum armpmu_attr_groups { |
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ARMPMU_ATTR_GROUP_COMMON, |
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ARMPMU_ATTR_GROUP_EVENTS, |
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ARMPMU_ATTR_GROUP_FORMATS, |
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ARMPMU_ATTR_GROUP_CAPS, |
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ARMPMU_NR_ATTR_GROUPS |
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}; |
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struct arm_pmu { |
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struct pmu pmu; |
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cpumask_t supported_cpus; |
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char *name; |
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int pmuver; |
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irqreturn_t (*handle_irq)(struct arm_pmu *pmu); |
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void (*enable)(struct perf_event *event); |
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void (*disable)(struct perf_event *event); |
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int (*get_event_idx)(struct pmu_hw_events *hw_events, |
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struct perf_event *event); |
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void (*clear_event_idx)(struct pmu_hw_events *hw_events, |
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struct perf_event *event); |
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int (*set_event_filter)(struct hw_perf_event *evt, |
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struct perf_event_attr *attr); |
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u64 (*read_counter)(struct perf_event *event); |
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void (*write_counter)(struct perf_event *event, u64 val); |
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void (*start)(struct arm_pmu *); |
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void (*stop)(struct arm_pmu *); |
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void (*reset)(void *); |
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int (*map_event)(struct perf_event *event); |
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int (*filter_match)(struct perf_event *event); |
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int num_events; |
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bool secure_access; /* 32-bit ARM only */ |
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#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40 |
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DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); |
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#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE 0x4000 |
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DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); |
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struct platform_device *plat_device; |
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struct pmu_hw_events __percpu *hw_events; |
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struct hlist_node node; |
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struct notifier_block cpu_pm_nb; |
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/* the attr_groups array must be NULL-terminated */ |
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const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1]; |
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/* store the PMMIR_EL1 to expose slots */ |
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u64 reg_pmmir; |
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/* Only to be used by ACPI probing code */ |
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unsigned long acpi_cpuid; |
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}; |
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#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) |
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u64 armpmu_event_update(struct perf_event *event); |
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int armpmu_event_set_period(struct perf_event *event); |
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int armpmu_map_event(struct perf_event *event, |
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const unsigned (*event_map)[PERF_COUNT_HW_MAX], |
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const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
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[PERF_COUNT_HW_CACHE_OP_MAX] |
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[PERF_COUNT_HW_CACHE_RESULT_MAX], |
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u32 raw_event_mask); |
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typedef int (*armpmu_init_fn)(struct arm_pmu *); |
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struct pmu_probe_info { |
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unsigned int cpuid; |
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unsigned int mask; |
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armpmu_init_fn init; |
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}; |
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#define PMU_PROBE(_cpuid, _mask, _fn) \ |
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{ \ |
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.cpuid = (_cpuid), \ |
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.mask = (_mask), \ |
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.init = (_fn), \ |
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} |
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#define ARM_PMU_PROBE(_cpuid, _fn) \ |
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PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn) |
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#define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK) |
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#define XSCALE_PMU_PROBE(_version, _fn) \ |
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PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn) |
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int arm_pmu_device_probe(struct platform_device *pdev, |
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const struct of_device_id *of_table, |
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const struct pmu_probe_info *probe_table); |
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#ifdef CONFIG_ACPI |
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int arm_pmu_acpi_probe(armpmu_init_fn init_fn); |
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#else |
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static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } |
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#endif |
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/* Internal functions only for core arm_pmu code */ |
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struct arm_pmu *armpmu_alloc(void); |
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struct arm_pmu *armpmu_alloc_atomic(void); |
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void armpmu_free(struct arm_pmu *pmu); |
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int armpmu_register(struct arm_pmu *pmu); |
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int armpmu_request_irq(int irq, int cpu); |
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void armpmu_free_irq(int irq, int cpu); |
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#define ARMV8_PMU_PDEV_NAME "armv8-pmu" |
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#endif /* CONFIG_ARM_PMU */ |
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#define ARMV8_SPE_PDEV_NAME "arm,spe-v1" |
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#endif /* __ARM_PMU_H__ */
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