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180 lines
5.8 KiB
180 lines
5.8 KiB
/* SPDX-License-Identifier: GPL-2.0 |
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* |
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* SuperH FLCTL nand controller |
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* |
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* Copyright © 2008 Renesas Solutions Corp. |
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*/ |
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#ifndef __SH_FLCTL_H__ |
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#define __SH_FLCTL_H__ |
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#include <linux/completion.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/pm_qos.h> |
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/* FLCTL registers */ |
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#define FLCMNCR(f) (f->reg + 0x0) |
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#define FLCMDCR(f) (f->reg + 0x4) |
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#define FLCMCDR(f) (f->reg + 0x8) |
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#define FLADR(f) (f->reg + 0xC) |
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#define FLADR2(f) (f->reg + 0x3C) |
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#define FLDATAR(f) (f->reg + 0x10) |
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#define FLDTCNTR(f) (f->reg + 0x14) |
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#define FLINTDMACR(f) (f->reg + 0x18) |
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#define FLBSYTMR(f) (f->reg + 0x1C) |
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#define FLBSYCNT(f) (f->reg + 0x20) |
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#define FLDTFIFO(f) (f->reg + 0x24) |
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#define FLECFIFO(f) (f->reg + 0x28) |
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#define FLTRCR(f) (f->reg + 0x2C) |
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#define FLHOLDCR(f) (f->reg + 0x38) |
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#define FL4ECCRESULT0(f) (f->reg + 0x80) |
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#define FL4ECCRESULT1(f) (f->reg + 0x84) |
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#define FL4ECCRESULT2(f) (f->reg + 0x88) |
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#define FL4ECCRESULT3(f) (f->reg + 0x8C) |
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#define FL4ECCCR(f) (f->reg + 0x90) |
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#define FL4ECCCNT(f) (f->reg + 0x94) |
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#define FLERRADR(f) (f->reg + 0x98) |
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/* FLCMNCR control bits */ |
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#define _4ECCCNTEN (0x1 << 24) |
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#define _4ECCEN (0x1 << 23) |
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#define _4ECCCORRECT (0x1 << 22) |
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#define SHBUSSEL (0x1 << 20) |
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#define SEL_16BIT (0x1 << 19) |
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#define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/ |
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#define QTSEL_E (0x1 << 17) |
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#define ENDIAN (0x1 << 16) /* 1 = little endian */ |
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#define FCKSEL_E (0x1 << 15) |
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#define ACM_SACCES_MODE (0x01 << 10) |
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#define NANWF_E (0x1 << 9) |
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#define SE_D (0x1 << 8) /* Spare area disable */ |
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#define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */ |
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#define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ |
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#define TYPESEL_SET (0x1 << 0) |
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/* |
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* Clock settings using the PULSEx registers from FLCMNCR |
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* |
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* Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E |
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* to control the clock divider used between the High-Speed Peripheral Clock |
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* and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit |
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* and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16 |
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* bit version the divider is seperate for the pulse width of high and low |
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* signals. |
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*/ |
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#define PULSE3 (0x1 << 27) |
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#define PULSE2 (0x1 << 17) |
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#define PULSE1 (0x1 << 15) |
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#define PULSE0 (0x1 << 9) |
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#define CLK_8B_0_5 PULSE1 |
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#define CLK_8B_1 0x0 |
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#define CLK_8B_1_5 (PULSE1 | PULSE2) |
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#define CLK_8B_2 PULSE0 |
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#define CLK_8B_3 (PULSE0 | PULSE1 | PULSE2) |
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#define CLK_8B_4 (PULSE0 | PULSE2) |
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#define CLK_16B_6L_2H PULSE0 |
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#define CLK_16B_9L_3H (PULSE0 | PULSE1 | PULSE2) |
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#define CLK_16B_12L_4H (PULSE0 | PULSE2) |
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/* FLCMDCR control bits */ |
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#define ADRCNT2_E (0x1 << 31) /* 5byte address enable */ |
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#define ADRMD_E (0x1 << 26) /* Sector address access */ |
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#define CDSRC_E (0x1 << 25) /* Data buffer selection */ |
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#define DOSR_E (0x1 << 24) /* Status read check */ |
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#define SELRW (0x1 << 21) /* 0:read 1:write */ |
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#define DOADR_E (0x1 << 20) /* Address stage execute */ |
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#define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */ |
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#define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */ |
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#define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */ |
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#define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */ |
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#define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */ |
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#define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */ |
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/* FLINTDMACR control bits */ |
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#define ESTERINTE (0x1 << 24) /* ECC error interrupt enable */ |
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#define AC1CLR (0x1 << 19) /* ECC FIFO clear */ |
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#define AC0CLR (0x1 << 18) /* Data FIFO clear */ |
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#define DREQ0EN (0x1 << 16) /* FLDTFIFODMA Request Enable */ |
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#define ECERB (0x1 << 9) /* ECC error */ |
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#define STERB (0x1 << 8) /* Status error */ |
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#define STERINTE (0x1 << 4) /* Status error enable */ |
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/* FLTRCR control bits */ |
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#define TRSTRT (0x1 << 0) /* translation start */ |
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#define TREND (0x1 << 1) /* translation end */ |
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/* |
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* FLHOLDCR control bits |
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* |
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* HOLDEN: Bus Occupancy Enable (inverted) |
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* Enable this bit when the external bus might be used in between transfers. |
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* If not set and the bus gets used by other modules, a deadlock occurs. |
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*/ |
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#define HOLDEN (0x1 << 0) |
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/* FL4ECCCR control bits */ |
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#define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */ |
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#define _4ECCEND (0x1 << 1) /* 4 symbols end */ |
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#define _4ECCEXST (0x1 << 0) /* 4 symbols exist */ |
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#define LOOP_TIMEOUT_MAX 0x00010000 |
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enum flctl_ecc_res_t { |
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FL_SUCCESS, |
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FL_REPAIRABLE, |
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FL_ERROR, |
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FL_TIMEOUT |
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}; |
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struct dma_chan; |
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struct sh_flctl { |
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struct nand_chip chip; |
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struct platform_device *pdev; |
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struct dev_pm_qos_request pm_qos; |
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void __iomem *reg; |
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resource_size_t fifo; |
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uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */ |
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int read_bytes; |
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unsigned int index; |
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int seqin_column; /* column in SEQIN cmd */ |
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int seqin_page_addr; /* page_addr in SEQIN cmd */ |
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uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */ |
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int erase1_page_addr; /* page_addr in ERASE1 cmd */ |
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uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ |
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uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ |
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uint32_t flcmncr_base; /* base value of FLCMNCR */ |
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uint32_t flintdmacr_base; /* irq enable bits */ |
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unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */ |
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unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ |
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unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */ |
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unsigned qos_request:1; /* QoS request to prevent deep power shutdown */ |
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/* DMA related objects */ |
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struct dma_chan *chan_fifo0_rx; |
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struct dma_chan *chan_fifo0_tx; |
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struct completion dma_complete; |
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}; |
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struct sh_flctl_platform_data { |
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struct mtd_partition *parts; |
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int nr_parts; |
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unsigned long flcmncr_val; |
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unsigned has_hwecc:1; |
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unsigned use_holden:1; |
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unsigned int slave_id_fifo0_tx; |
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unsigned int slave_id_fifo0_rx; |
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}; |
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static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) |
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{ |
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return container_of(mtd_to_nand(mtdinfo), struct sh_flctl, chip); |
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} |
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#endif /* __SH_FLCTL_H__ */
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