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128 lines
5.0 KiB
128 lines
5.0 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __LIS3LV02D_H_ |
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#define __LIS3LV02D_H_ |
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/** |
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* struct lis3lv02d_platform_data - lis3 chip family platform data |
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* @click_flags: Click detection unit configuration |
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* @click_thresh_x: Click detection unit x axis threshold |
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* @click_thresh_y: Click detection unit y axis threshold |
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* @click_thresh_z: Click detection unit z axis threshold |
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* @click_time_limit: Click detection unit time parameter |
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* @click_latency: Click detection unit latency parameter |
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* @click_window: Click detection unit window parameter |
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* @irq_cfg: On chip irq source and type configuration (click / |
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* data available / wake up, open drain, polarity) |
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* @irq_flags1: Additional irq triggering flags for irq channel 0 |
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* @irq_flags2: Additional irq triggering flags for irq channel 1 |
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* @duration1: Wake up unit 1 duration parameter |
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* @duration2: Wake up unit 2 duration parameter |
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* @wakeup_flags: Wake up unit 1 flags |
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* @wakeup_thresh: Wake up unit 1 threshold value |
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* @wakeup_flags2: Wake up unit 2 flags |
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* @wakeup_thresh2: Wake up unit 2 threshold value |
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* @hipass_ctrl: High pass filter control (enable / disable, cut off |
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* frequency) |
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* @axis_x: Sensor orientation remapping for x-axis |
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* @axis_y: Sensor orientation remapping for y-axis |
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* @axis_z: Sensor orientation remapping for z-axis |
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* @driver_features: Enable bits for different features. Disabled by default |
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* @default_rate: Default sampling rate. 0 means reset default |
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* @setup_resources: Interrupt line setup call back function |
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* @release_resources: Interrupt line release call back function |
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* @st_min_limits[3]: Selftest acceptance minimum values |
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* @st_max_limits[3]: Selftest acceptance maximum values |
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* @irq2: Irq line 2 number |
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* |
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* Platform data is used to setup the sensor chip. Meaning of the different |
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* chip features can be found from the data sheet. It is publicly available |
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* at www.st.com web pages. Currently the platform data is used |
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* only for the 8 bit device. The 8 bit device has two wake up / free fall |
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* detection units and click detection unit. There are plenty of ways to |
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* configure the chip which makes is quite hard to explain deeper meaning of |
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* the fields here. Behaviour of the detection blocks varies heavily depending |
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* on the configuration. For example, interrupt detection block can use high |
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* pass filtered data which makes it react to the changes in the acceleration. |
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* Irq_flags can be used to enable interrupt detection on the both edges. |
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* With proper chip configuration this produces interrupt when some trigger |
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* starts and when it goes away. |
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*/ |
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struct lis3lv02d_platform_data { |
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/* please note: the 'click' feature is only supported for |
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* LIS[32]02DL variants of the chip and will be ignored for |
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* others */ |
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#define LIS3_CLICK_SINGLE_X (1 << 0) |
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#define LIS3_CLICK_DOUBLE_X (1 << 1) |
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#define LIS3_CLICK_SINGLE_Y (1 << 2) |
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#define LIS3_CLICK_DOUBLE_Y (1 << 3) |
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#define LIS3_CLICK_SINGLE_Z (1 << 4) |
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#define LIS3_CLICK_DOUBLE_Z (1 << 5) |
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unsigned char click_flags; |
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unsigned char click_thresh_x; |
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unsigned char click_thresh_y; |
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unsigned char click_thresh_z; |
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unsigned char click_time_limit; |
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unsigned char click_latency; |
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unsigned char click_window; |
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#define LIS3_IRQ1_DISABLE (0 << 0) |
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#define LIS3_IRQ1_FF_WU_1 (1 << 0) |
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#define LIS3_IRQ1_FF_WU_2 (2 << 0) |
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#define LIS3_IRQ1_FF_WU_12 (3 << 0) |
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#define LIS3_IRQ1_DATA_READY (4 << 0) |
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#define LIS3_IRQ1_CLICK (7 << 0) |
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#define LIS3_IRQ1_MASK (7 << 0) |
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#define LIS3_IRQ2_DISABLE (0 << 3) |
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#define LIS3_IRQ2_FF_WU_1 (1 << 3) |
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#define LIS3_IRQ2_FF_WU_2 (2 << 3) |
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#define LIS3_IRQ2_FF_WU_12 (3 << 3) |
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#define LIS3_IRQ2_DATA_READY (4 << 3) |
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#define LIS3_IRQ2_CLICK (7 << 3) |
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#define LIS3_IRQ2_MASK (7 << 3) |
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#define LIS3_IRQ_OPEN_DRAIN (1 << 6) |
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#define LIS3_IRQ_ACTIVE_LOW (1 << 7) |
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unsigned char irq_cfg; |
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unsigned char irq_flags1; /* Additional irq edge / level flags */ |
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unsigned char irq_flags2; /* Additional irq edge / level flags */ |
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unsigned char duration1; |
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unsigned char duration2; |
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#define LIS3_WAKEUP_X_LO (1 << 0) |
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#define LIS3_WAKEUP_X_HI (1 << 1) |
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#define LIS3_WAKEUP_Y_LO (1 << 2) |
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#define LIS3_WAKEUP_Y_HI (1 << 3) |
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#define LIS3_WAKEUP_Z_LO (1 << 4) |
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#define LIS3_WAKEUP_Z_HI (1 << 5) |
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unsigned char wakeup_flags; |
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unsigned char wakeup_thresh; |
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unsigned char wakeup_flags2; |
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unsigned char wakeup_thresh2; |
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#define LIS3_HIPASS_CUTFF_8HZ 0 |
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#define LIS3_HIPASS_CUTFF_4HZ 1 |
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#define LIS3_HIPASS_CUTFF_2HZ 2 |
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#define LIS3_HIPASS_CUTFF_1HZ 3 |
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#define LIS3_HIPASS1_DISABLE (1 << 2) |
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#define LIS3_HIPASS2_DISABLE (1 << 3) |
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unsigned char hipass_ctrl; |
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#define LIS3_NO_MAP 0 |
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#define LIS3_DEV_X 1 |
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#define LIS3_DEV_Y 2 |
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#define LIS3_DEV_Z 3 |
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#define LIS3_INV_DEV_X -1 |
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#define LIS3_INV_DEV_Y -2 |
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#define LIS3_INV_DEV_Z -3 |
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s8 axis_x; |
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s8 axis_y; |
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s8 axis_z; |
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#define LIS3_USE_BLOCK_READ 0x02 |
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u16 driver_features; |
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int default_rate; |
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int (*setup_resources)(void); |
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int (*release_resources)(void); |
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/* Limits for selftest are specified in chip data sheet */ |
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s16 st_min_limits[3]; /* min pass limit x, y, z */ |
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s16 st_max_limits[3]; /* max pass limit x, y, z */ |
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int irq2; |
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}; |
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#endif /* __LIS3LV02D_H_ */
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