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166 lines
5.4 KiB
166 lines
5.4 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* include/linux/irqchip/arm-gic.h |
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* |
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* Copyright (C) 2002 ARM Limited, All Rights Reserved. |
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*/ |
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#ifndef __LINUX_IRQCHIP_ARM_GIC_H |
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#define __LINUX_IRQCHIP_ARM_GIC_H |
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#define GIC_CPU_CTRL 0x00 |
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#define GIC_CPU_PRIMASK 0x04 |
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#define GIC_CPU_BINPOINT 0x08 |
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#define GIC_CPU_INTACK 0x0c |
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#define GIC_CPU_EOI 0x10 |
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#define GIC_CPU_RUNNINGPRI 0x14 |
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#define GIC_CPU_HIGHPRI 0x18 |
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#define GIC_CPU_ALIAS_BINPOINT 0x1c |
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#define GIC_CPU_ACTIVEPRIO 0xd0 |
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#define GIC_CPU_IDENT 0xfc |
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#define GIC_CPU_DEACTIVATE 0x1000 |
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#define GICC_ENABLE 0x1 |
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#define GICC_INT_PRI_THRESHOLD 0xf0 |
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#define GIC_CPU_CTRL_EnableGrp0_SHIFT 0 |
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#define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT) |
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#define GIC_CPU_CTRL_EnableGrp1_SHIFT 1 |
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#define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT) |
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#define GIC_CPU_CTRL_AckCtl_SHIFT 2 |
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#define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT) |
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#define GIC_CPU_CTRL_FIQEn_SHIFT 3 |
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#define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT) |
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#define GIC_CPU_CTRL_CBPR_SHIFT 4 |
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#define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT) |
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#define GIC_CPU_CTRL_EOImodeNS_SHIFT 9 |
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#define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT) |
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#define GICC_IAR_INT_ID_MASK 0x3ff |
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#define GICC_INT_SPURIOUS 1023 |
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#define GICC_DIS_BYPASS_MASK 0x1e0 |
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#define GIC_DIST_CTRL 0x000 |
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#define GIC_DIST_CTR 0x004 |
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#define GIC_DIST_IIDR 0x008 |
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#define GIC_DIST_IGROUP 0x080 |
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#define GIC_DIST_ENABLE_SET 0x100 |
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#define GIC_DIST_ENABLE_CLEAR 0x180 |
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#define GIC_DIST_PENDING_SET 0x200 |
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#define GIC_DIST_PENDING_CLEAR 0x280 |
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#define GIC_DIST_ACTIVE_SET 0x300 |
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#define GIC_DIST_ACTIVE_CLEAR 0x380 |
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#define GIC_DIST_PRI 0x400 |
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#define GIC_DIST_TARGET 0x800 |
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#define GIC_DIST_CONFIG 0xc00 |
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#define GIC_DIST_SOFTINT 0xf00 |
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#define GIC_DIST_SGI_PENDING_CLEAR 0xf10 |
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#define GIC_DIST_SGI_PENDING_SET 0xf20 |
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#define GICD_ENABLE 0x1 |
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#define GICD_DISABLE 0x0 |
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#define GICD_INT_ACTLOW_LVLTRIG 0x0 |
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#define GICD_INT_EN_CLR_X32 0xffffffff |
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#define GICD_INT_EN_SET_SGI 0x0000ffff |
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#define GICD_INT_EN_CLR_PPI 0xffff0000 |
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#define GICD_IIDR_IMPLEMENTER_SHIFT 0 |
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#define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) |
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#define GICD_IIDR_REVISION_SHIFT 12 |
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#define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) |
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#define GICD_IIDR_VARIANT_SHIFT 16 |
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#define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) |
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#define GICD_IIDR_PRODUCT_ID_SHIFT 24 |
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#define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) |
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#define GICH_HCR 0x0 |
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#define GICH_VTR 0x4 |
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#define GICH_VMCR 0x8 |
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#define GICH_MISR 0x10 |
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#define GICH_EISR0 0x20 |
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#define GICH_EISR1 0x24 |
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#define GICH_ELRSR0 0x30 |
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#define GICH_ELRSR1 0x34 |
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#define GICH_APR 0xf0 |
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#define GICH_LR0 0x100 |
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#define GICH_HCR_EN (1 << 0) |
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#define GICH_HCR_UIE (1 << 1) |
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#define GICH_HCR_NPIE (1 << 3) |
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#define GICH_LR_VIRTUALID (0x3ff << 0) |
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#define GICH_LR_PHYSID_CPUID_SHIFT (10) |
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#define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) |
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#define GICH_LR_PRIORITY_SHIFT 23 |
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#define GICH_LR_STATE (3 << 28) |
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#define GICH_LR_PENDING_BIT (1 << 28) |
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#define GICH_LR_ACTIVE_BIT (1 << 29) |
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#define GICH_LR_EOI (1 << 19) |
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#define GICH_LR_GROUP1 (1 << 30) |
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#define GICH_LR_HW (1 << 31) |
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#define GICH_VMCR_ENABLE_GRP0_SHIFT 0 |
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#define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT) |
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#define GICH_VMCR_ENABLE_GRP1_SHIFT 1 |
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#define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT) |
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#define GICH_VMCR_ACK_CTL_SHIFT 2 |
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#define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT) |
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#define GICH_VMCR_FIQ_EN_SHIFT 3 |
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#define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT) |
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#define GICH_VMCR_CBPR_SHIFT 4 |
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#define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT) |
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#define GICH_VMCR_EOI_MODE_SHIFT 9 |
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#define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT) |
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#define GICH_VMCR_PRIMASK_SHIFT 27 |
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#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) |
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#define GICH_VMCR_BINPOINT_SHIFT 21 |
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#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) |
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#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 |
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#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) |
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#define GICH_MISR_EOI (1 << 0) |
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#define GICH_MISR_U (1 << 1) |
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#define GICV_PMR_PRIORITY_SHIFT 3 |
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#define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT) |
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#ifndef __ASSEMBLY__ |
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#include <linux/irqdomain.h> |
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struct device_node; |
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struct gic_chip_data; |
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void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
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int gic_cpu_if_down(unsigned int gic_nr); |
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void gic_cpu_save(struct gic_chip_data *gic); |
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void gic_cpu_restore(struct gic_chip_data *gic); |
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void gic_dist_save(struct gic_chip_data *gic); |
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void gic_dist_restore(struct gic_chip_data *gic); |
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/* |
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* Subdrivers that need some preparatory work can initialize their |
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* chips and call this to register their GICs. |
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*/ |
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int gic_of_init(struct device_node *node, struct device_node *parent); |
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/* |
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* Initialises and registers a non-root or child GIC chip. Memory for |
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* the gic_chip_data structure is dynamically allocated. |
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*/ |
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int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq); |
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/* |
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* Legacy platforms not converted to DT yet must use this to init |
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* their GIC |
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*/ |
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void gic_init(void __iomem *dist , void __iomem *cpu); |
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void gic_send_sgi(unsigned int cpu_id, unsigned int irq); |
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int gic_get_cpu_id(unsigned int cpu); |
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void gic_migrate_target(unsigned int new_cpu_id); |
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unsigned long gic_get_sgir_physaddr(void); |
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#endif /* __ASSEMBLY */ |
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#endif
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