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350 lines
9.9 KiB
350 lines
9.9 KiB
/* |
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* Private header for the MPC52xx processor BestComm driver |
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* |
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* By private, we mean that driver should not use it directly. It's meant |
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* to be used by the BestComm engine driver itself and by the intermediate |
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* layer between the core and the drivers. |
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* |
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* Copyright (C) 2006 Sylvain Munaut <[email protected]> |
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* Copyright (C) 2005 Varma Electronics Oy, |
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* ( by Andrey Volkov <[email protected]> ) |
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* Copyright (C) 2003-2004 MontaVista, Software, Inc. |
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* ( by Dale Farnsworth <[email protected]> ) |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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#ifndef __BESTCOMM_PRIV_H__ |
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#define __BESTCOMM_PRIV_H__ |
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#include <linux/spinlock.h> |
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#include <linux/of.h> |
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#include <asm/io.h> |
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#include <asm/mpc52xx.h> |
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#include "sram.h" |
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/* ======================================================================== */ |
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/* Engine related stuff */ |
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/* ======================================================================== */ |
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/* Zones sizes and needed alignments */ |
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#define BCOM_MAX_TASKS 16 |
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#define BCOM_MAX_VAR 24 |
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#define BCOM_MAX_INC 8 |
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#define BCOM_MAX_FDT 64 |
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#define BCOM_MAX_CTX 20 |
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#define BCOM_CTX_SIZE (BCOM_MAX_CTX * sizeof(u32)) |
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#define BCOM_CTX_ALIGN 0x100 |
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#define BCOM_VAR_SIZE (BCOM_MAX_VAR * sizeof(u32)) |
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#define BCOM_INC_SIZE (BCOM_MAX_INC * sizeof(u32)) |
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#define BCOM_VAR_ALIGN 0x80 |
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#define BCOM_FDT_SIZE (BCOM_MAX_FDT * sizeof(u32)) |
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#define BCOM_FDT_ALIGN 0x100 |
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/** |
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* struct bcom_tdt - Task Descriptor Table Entry |
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* |
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*/ |
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struct bcom_tdt { |
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u32 start; |
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u32 stop; |
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u32 var; |
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u32 fdt; |
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u32 exec_status; /* used internally by BestComm engine */ |
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u32 mvtp; /* used internally by BestComm engine */ |
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u32 context; |
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u32 litbase; |
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}; |
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/** |
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* struct bcom_engine |
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* |
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* This holds all info needed globaly to handle the engine |
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*/ |
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struct bcom_engine { |
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struct device_node *ofnode; |
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struct mpc52xx_sdma __iomem *regs; |
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phys_addr_t regs_base; |
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struct bcom_tdt *tdt; |
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u32 *ctx; |
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u32 *var; |
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u32 *fdt; |
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spinlock_t lock; |
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}; |
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extern struct bcom_engine *bcom_eng; |
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/* ======================================================================== */ |
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/* Tasks related stuff */ |
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/* ======================================================================== */ |
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/* Tasks image header */ |
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#define BCOM_TASK_MAGIC 0x4243544B /* 'BCTK' */ |
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struct bcom_task_header { |
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u32 magic; |
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u8 desc_size; /* the size fields */ |
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u8 var_size; /* are given in number */ |
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u8 inc_size; /* of 32-bits words */ |
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u8 first_var; |
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u8 reserved[8]; |
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}; |
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/* Descriptors structure & co */ |
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#define BCOM_DESC_NOP 0x000001f8 |
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#define BCOM_LCD_MASK 0x80000000 |
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#define BCOM_DRD_EXTENDED 0x40000000 |
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#define BCOM_DRD_INITIATOR_SHIFT 21 |
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/* Tasks pragma */ |
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#define BCOM_PRAGMA_BIT_RSV 7 /* reserved pragma bit */ |
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#define BCOM_PRAGMA_BIT_PRECISE_INC 6 /* increment 0=when possible, */ |
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/* 1=iter end */ |
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#define BCOM_PRAGMA_BIT_RST_ERROR_NO 5 /* don't reset errors on */ |
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/* task enable */ |
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#define BCOM_PRAGMA_BIT_PACK 4 /* pack data enable */ |
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#define BCOM_PRAGMA_BIT_INTEGER 3 /* data alignment */ |
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/* 0=frac(msb), 1=int(lsb) */ |
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#define BCOM_PRAGMA_BIT_SPECREAD 2 /* XLB speculative read */ |
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#define BCOM_PRAGMA_BIT_CW 1 /* write line buffer enable */ |
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#define BCOM_PRAGMA_BIT_RL 0 /* read line buffer enable */ |
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/* Looks like XLB speculative read generates XLB errors when a buffer |
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* is at the end of the physical memory. i.e. when accessing the |
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* lasts words, the engine tries to prefetch the next but there is no |
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* next ... |
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*/ |
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#define BCOM_STD_PRAGMA ((0 << BCOM_PRAGMA_BIT_RSV) | \ |
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(0 << BCOM_PRAGMA_BIT_PRECISE_INC) | \ |
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(0 << BCOM_PRAGMA_BIT_RST_ERROR_NO) | \ |
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(0 << BCOM_PRAGMA_BIT_PACK) | \ |
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(0 << BCOM_PRAGMA_BIT_INTEGER) | \ |
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(0 << BCOM_PRAGMA_BIT_SPECREAD) | \ |
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(1 << BCOM_PRAGMA_BIT_CW) | \ |
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(1 << BCOM_PRAGMA_BIT_RL)) |
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#define BCOM_PCI_PRAGMA ((0 << BCOM_PRAGMA_BIT_RSV) | \ |
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(0 << BCOM_PRAGMA_BIT_PRECISE_INC) | \ |
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(0 << BCOM_PRAGMA_BIT_RST_ERROR_NO) | \ |
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(0 << BCOM_PRAGMA_BIT_PACK) | \ |
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(1 << BCOM_PRAGMA_BIT_INTEGER) | \ |
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(0 << BCOM_PRAGMA_BIT_SPECREAD) | \ |
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(1 << BCOM_PRAGMA_BIT_CW) | \ |
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(1 << BCOM_PRAGMA_BIT_RL)) |
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#define BCOM_ATA_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_CRC16_DP_0_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_CRC16_DP_1_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_FEC_RX_BD_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_FEC_TX_BD_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_DP_0_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_DP_1_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_DP_2_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_DP_3_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_DP_BD_0_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_DP_BD_1_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_RX_BD_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_TX_BD_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_GEN_LPC_PRAGMA BCOM_STD_PRAGMA |
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#define BCOM_PCI_RX_PRAGMA BCOM_PCI_PRAGMA |
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#define BCOM_PCI_TX_PRAGMA BCOM_PCI_PRAGMA |
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/* Initiators number */ |
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#define BCOM_INITIATOR_ALWAYS 0 |
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#define BCOM_INITIATOR_SCTMR_0 1 |
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#define BCOM_INITIATOR_SCTMR_1 2 |
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#define BCOM_INITIATOR_FEC_RX 3 |
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#define BCOM_INITIATOR_FEC_TX 4 |
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#define BCOM_INITIATOR_ATA_RX 5 |
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#define BCOM_INITIATOR_ATA_TX 6 |
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#define BCOM_INITIATOR_SCPCI_RX 7 |
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#define BCOM_INITIATOR_SCPCI_TX 8 |
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#define BCOM_INITIATOR_PSC3_RX 9 |
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#define BCOM_INITIATOR_PSC3_TX 10 |
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#define BCOM_INITIATOR_PSC2_RX 11 |
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#define BCOM_INITIATOR_PSC2_TX 12 |
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#define BCOM_INITIATOR_PSC1_RX 13 |
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#define BCOM_INITIATOR_PSC1_TX 14 |
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#define BCOM_INITIATOR_SCTMR_2 15 |
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#define BCOM_INITIATOR_SCLPC 16 |
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#define BCOM_INITIATOR_PSC5_RX 17 |
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#define BCOM_INITIATOR_PSC5_TX 18 |
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#define BCOM_INITIATOR_PSC4_RX 19 |
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#define BCOM_INITIATOR_PSC4_TX 20 |
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#define BCOM_INITIATOR_I2C2_RX 21 |
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#define BCOM_INITIATOR_I2C2_TX 22 |
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#define BCOM_INITIATOR_I2C1_RX 23 |
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#define BCOM_INITIATOR_I2C1_TX 24 |
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#define BCOM_INITIATOR_PSC6_RX 25 |
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#define BCOM_INITIATOR_PSC6_TX 26 |
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#define BCOM_INITIATOR_IRDA_RX 25 |
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#define BCOM_INITIATOR_IRDA_TX 26 |
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#define BCOM_INITIATOR_SCTMR_3 27 |
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#define BCOM_INITIATOR_SCTMR_4 28 |
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#define BCOM_INITIATOR_SCTMR_5 29 |
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#define BCOM_INITIATOR_SCTMR_6 30 |
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#define BCOM_INITIATOR_SCTMR_7 31 |
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/* Initiators priorities */ |
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#define BCOM_IPR_ALWAYS 7 |
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#define BCOM_IPR_SCTMR_0 2 |
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#define BCOM_IPR_SCTMR_1 2 |
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#define BCOM_IPR_FEC_RX 6 |
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#define BCOM_IPR_FEC_TX 5 |
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#define BCOM_IPR_ATA_RX 7 |
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#define BCOM_IPR_ATA_TX 7 |
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#define BCOM_IPR_SCPCI_RX 2 |
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#define BCOM_IPR_SCPCI_TX 2 |
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#define BCOM_IPR_PSC3_RX 2 |
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#define BCOM_IPR_PSC3_TX 2 |
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#define BCOM_IPR_PSC2_RX 2 |
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#define BCOM_IPR_PSC2_TX 2 |
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#define BCOM_IPR_PSC1_RX 2 |
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#define BCOM_IPR_PSC1_TX 2 |
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#define BCOM_IPR_SCTMR_2 2 |
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#define BCOM_IPR_SCLPC 2 |
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#define BCOM_IPR_PSC5_RX 2 |
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#define BCOM_IPR_PSC5_TX 2 |
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#define BCOM_IPR_PSC4_RX 2 |
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#define BCOM_IPR_PSC4_TX 2 |
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#define BCOM_IPR_I2C2_RX 2 |
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#define BCOM_IPR_I2C2_TX 2 |
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#define BCOM_IPR_I2C1_RX 2 |
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#define BCOM_IPR_I2C1_TX 2 |
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#define BCOM_IPR_PSC6_RX 2 |
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#define BCOM_IPR_PSC6_TX 2 |
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#define BCOM_IPR_IRDA_RX 2 |
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#define BCOM_IPR_IRDA_TX 2 |
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#define BCOM_IPR_SCTMR_3 2 |
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#define BCOM_IPR_SCTMR_4 2 |
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#define BCOM_IPR_SCTMR_5 2 |
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#define BCOM_IPR_SCTMR_6 2 |
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#define BCOM_IPR_SCTMR_7 2 |
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/* ======================================================================== */ |
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/* API */ |
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/* ======================================================================== */ |
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extern struct bcom_task *bcom_task_alloc(int bd_count, int bd_size, int priv_size); |
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extern void bcom_task_free(struct bcom_task *tsk); |
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extern int bcom_load_image(int task, u32 *task_image); |
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extern void bcom_set_initiator(int task, int initiator); |
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#define TASK_ENABLE 0x8000 |
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/** |
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* bcom_disable_prefetch - Hook to disable bus prefetching |
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* |
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* ATA DMA and the original MPC5200 need this due to silicon bugs. At the |
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* moment disabling prefetch is a one-way street. There is no mechanism |
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* in place to turn prefetch back on after it has been disabled. There is |
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* no reason it couldn't be done, it would just be more complex to implement. |
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*/ |
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static inline void bcom_disable_prefetch(void) |
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{ |
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u16 regval; |
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regval = in_be16(&bcom_eng->regs->PtdCntrl); |
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out_be16(&bcom_eng->regs->PtdCntrl, regval | 1); |
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}; |
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static inline void |
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bcom_enable_task(int task) |
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{ |
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u16 reg; |
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reg = in_be16(&bcom_eng->regs->tcr[task]); |
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out_be16(&bcom_eng->regs->tcr[task], reg | TASK_ENABLE); |
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} |
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static inline void |
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bcom_disable_task(int task) |
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{ |
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u16 reg = in_be16(&bcom_eng->regs->tcr[task]); |
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out_be16(&bcom_eng->regs->tcr[task], reg & ~TASK_ENABLE); |
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} |
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static inline u32 * |
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bcom_task_desc(int task) |
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{ |
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return bcom_sram_pa2va(bcom_eng->tdt[task].start); |
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} |
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static inline int |
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bcom_task_num_descs(int task) |
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{ |
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return (bcom_eng->tdt[task].stop - bcom_eng->tdt[task].start)/sizeof(u32) + 1; |
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} |
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static inline u32 * |
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bcom_task_var(int task) |
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{ |
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return bcom_sram_pa2va(bcom_eng->tdt[task].var); |
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} |
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static inline u32 * |
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bcom_task_inc(int task) |
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{ |
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return &bcom_task_var(task)[BCOM_MAX_VAR]; |
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} |
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static inline int |
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bcom_drd_is_extended(u32 desc) |
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{ |
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return (desc) & BCOM_DRD_EXTENDED; |
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} |
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static inline int |
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bcom_desc_is_drd(u32 desc) |
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{ |
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return !(desc & BCOM_LCD_MASK) && desc != BCOM_DESC_NOP; |
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} |
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static inline int |
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bcom_desc_initiator(u32 desc) |
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{ |
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return (desc >> BCOM_DRD_INITIATOR_SHIFT) & 0x1f; |
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} |
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static inline void |
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bcom_set_desc_initiator(u32 *desc, int initiator) |
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{ |
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*desc = (*desc & ~(0x1f << BCOM_DRD_INITIATOR_SHIFT)) | |
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((initiator & 0x1f) << BCOM_DRD_INITIATOR_SHIFT); |
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} |
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static inline void |
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bcom_set_task_pragma(int task, int pragma) |
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{ |
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u32 *fdt = &bcom_eng->tdt[task].fdt; |
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*fdt = (*fdt & ~0xff) | pragma; |
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} |
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static inline void |
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bcom_set_task_auto_start(int task, int next_task) |
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{ |
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u16 __iomem *tcr = &bcom_eng->regs->tcr[task]; |
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out_be16(tcr, (in_be16(tcr) & ~0xff) | 0x00c0 | next_task); |
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} |
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static inline void |
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bcom_set_tcr_initiator(int task, int initiator) |
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{ |
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u16 __iomem *tcr = &bcom_eng->regs->tcr[task]; |
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out_be16(tcr, (in_be16(tcr) & ~0x1f00) | ((initiator & 0x1f) << 8)); |
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} |
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#endif /* __BESTCOMM_PRIV_H__ */ |
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