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537 lines
14 KiB
537 lines
14 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Xilinx Zynq MPSoC Firmware layer |
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* |
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* Copyright (C) 2014-2019 Xilinx |
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* |
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* Michal Simek <[email protected]> |
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* Davorin Mista <[email protected]> |
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* Jolly Shah <[email protected]> |
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* Rajan Vaja <[email protected]> |
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*/ |
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#ifndef __FIRMWARE_ZYNQMP_H__ |
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#define __FIRMWARE_ZYNQMP_H__ |
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#include <linux/err.h> |
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#define ZYNQMP_PM_VERSION_MAJOR 1 |
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#define ZYNQMP_PM_VERSION_MINOR 0 |
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#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \ |
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ZYNQMP_PM_VERSION_MINOR) |
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#define ZYNQMP_TZ_VERSION_MAJOR 1 |
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#define ZYNQMP_TZ_VERSION_MINOR 0 |
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#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ |
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ZYNQMP_TZ_VERSION_MINOR) |
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/* SMC SIP service Call Function Identifier Prefix */ |
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#define PM_SIP_SVC 0xC2000000 |
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#define PM_GET_TRUSTZONE_VERSION 0xa03 |
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#define PM_SET_SUSPEND_MODE 0xa02 |
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#define GET_CALLBACK_DATA 0xa01 |
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/* Number of 32bits values in payload */ |
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#define PAYLOAD_ARG_CNT 4U |
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/* Number of arguments for a callback */ |
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#define CB_ARG_CNT 4 |
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/* Payload size (consists of callback API ID + arguments) */ |
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#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1) |
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#define ZYNQMP_PM_MAX_QOS 100U |
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#define GSS_NUM_REGS (4) |
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/* Node capabilities */ |
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#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U |
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#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U |
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#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U |
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#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U |
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/* |
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* Firmware FPGA Manager flags |
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* XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration |
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* XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration |
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*/ |
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#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U |
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#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) |
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enum pm_api_id { |
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PM_GET_API_VERSION = 1, |
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PM_SYSTEM_SHUTDOWN = 12, |
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PM_REQUEST_NODE = 13, |
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PM_RELEASE_NODE = 14, |
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PM_SET_REQUIREMENT = 15, |
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PM_RESET_ASSERT = 17, |
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PM_RESET_GET_STATUS = 18, |
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PM_PM_INIT_FINALIZE = 21, |
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PM_FPGA_LOAD = 22, |
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PM_FPGA_GET_STATUS = 23, |
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PM_GET_CHIPID = 24, |
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PM_IOCTL = 34, |
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PM_QUERY_DATA = 35, |
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PM_CLOCK_ENABLE = 36, |
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PM_CLOCK_DISABLE = 37, |
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PM_CLOCK_GETSTATE = 38, |
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PM_CLOCK_SETDIVIDER = 39, |
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PM_CLOCK_GETDIVIDER = 40, |
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PM_CLOCK_SETRATE = 41, |
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PM_CLOCK_GETRATE = 42, |
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PM_CLOCK_SETPARENT = 43, |
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PM_CLOCK_GETPARENT = 44, |
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PM_SECURE_AES = 47, |
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PM_FEATURE_CHECK = 63, |
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}; |
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/* PMU-FW return status codes */ |
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enum pm_ret_status { |
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XST_PM_SUCCESS = 0, |
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XST_PM_NO_FEATURE = 19, |
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XST_PM_INTERNAL = 2000, |
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XST_PM_CONFLICT = 2001, |
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XST_PM_NO_ACCESS = 2002, |
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XST_PM_INVALID_NODE = 2003, |
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XST_PM_DOUBLE_REQ = 2004, |
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XST_PM_ABORT_SUSPEND = 2005, |
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XST_PM_MULT_USER = 2008, |
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}; |
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enum pm_ioctl_id { |
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IOCTL_SD_DLL_RESET = 6, |
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IOCTL_SET_SD_TAPDELAY = 7, |
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IOCTL_SET_PLL_FRAC_MODE = 8, |
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IOCTL_GET_PLL_FRAC_MODE = 9, |
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IOCTL_SET_PLL_FRAC_DATA = 10, |
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IOCTL_GET_PLL_FRAC_DATA = 11, |
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IOCTL_WRITE_GGS = 12, |
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IOCTL_READ_GGS = 13, |
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IOCTL_WRITE_PGGS = 14, |
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IOCTL_READ_PGGS = 15, |
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/* Set healthy bit value */ |
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IOCTL_SET_BOOT_HEALTH_STATUS = 17, |
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}; |
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enum pm_query_id { |
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PM_QID_INVALID = 0, |
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PM_QID_CLOCK_GET_NAME = 1, |
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PM_QID_CLOCK_GET_TOPOLOGY = 2, |
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PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, |
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PM_QID_CLOCK_GET_PARENTS = 4, |
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PM_QID_CLOCK_GET_ATTRIBUTES = 5, |
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PM_QID_CLOCK_GET_NUM_CLOCKS = 12, |
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PM_QID_CLOCK_GET_MAX_DIVISOR = 13, |
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}; |
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enum zynqmp_pm_reset_action { |
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PM_RESET_ACTION_RELEASE = 0, |
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PM_RESET_ACTION_ASSERT = 1, |
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PM_RESET_ACTION_PULSE = 2, |
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}; |
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enum zynqmp_pm_reset { |
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ZYNQMP_PM_RESET_START = 1000, |
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ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, |
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ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, |
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ZYNQMP_PM_RESET_PCIE_CTRL = 1002, |
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ZYNQMP_PM_RESET_DP = 1003, |
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ZYNQMP_PM_RESET_SWDT_CRF = 1004, |
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ZYNQMP_PM_RESET_AFI_FM5 = 1005, |
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ZYNQMP_PM_RESET_AFI_FM4 = 1006, |
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ZYNQMP_PM_RESET_AFI_FM3 = 1007, |
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ZYNQMP_PM_RESET_AFI_FM2 = 1008, |
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ZYNQMP_PM_RESET_AFI_FM1 = 1009, |
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ZYNQMP_PM_RESET_AFI_FM0 = 1010, |
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ZYNQMP_PM_RESET_GDMA = 1011, |
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ZYNQMP_PM_RESET_GPU_PP1 = 1012, |
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ZYNQMP_PM_RESET_GPU_PP0 = 1013, |
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ZYNQMP_PM_RESET_GPU = 1014, |
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ZYNQMP_PM_RESET_GT = 1015, |
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ZYNQMP_PM_RESET_SATA = 1016, |
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ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, |
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ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, |
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ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, |
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ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, |
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ZYNQMP_PM_RESET_APU_L2 = 1021, |
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ZYNQMP_PM_RESET_ACPU3 = 1022, |
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ZYNQMP_PM_RESET_ACPU2 = 1023, |
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ZYNQMP_PM_RESET_ACPU1 = 1024, |
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ZYNQMP_PM_RESET_ACPU0 = 1025, |
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ZYNQMP_PM_RESET_DDR = 1026, |
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ZYNQMP_PM_RESET_APM_FPD = 1027, |
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ZYNQMP_PM_RESET_SOFT = 1028, |
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ZYNQMP_PM_RESET_GEM0 = 1029, |
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ZYNQMP_PM_RESET_GEM1 = 1030, |
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ZYNQMP_PM_RESET_GEM2 = 1031, |
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ZYNQMP_PM_RESET_GEM3 = 1032, |
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ZYNQMP_PM_RESET_QSPI = 1033, |
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ZYNQMP_PM_RESET_UART0 = 1034, |
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ZYNQMP_PM_RESET_UART1 = 1035, |
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ZYNQMP_PM_RESET_SPI0 = 1036, |
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ZYNQMP_PM_RESET_SPI1 = 1037, |
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ZYNQMP_PM_RESET_SDIO0 = 1038, |
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ZYNQMP_PM_RESET_SDIO1 = 1039, |
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ZYNQMP_PM_RESET_CAN0 = 1040, |
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ZYNQMP_PM_RESET_CAN1 = 1041, |
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ZYNQMP_PM_RESET_I2C0 = 1042, |
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ZYNQMP_PM_RESET_I2C1 = 1043, |
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ZYNQMP_PM_RESET_TTC0 = 1044, |
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ZYNQMP_PM_RESET_TTC1 = 1045, |
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ZYNQMP_PM_RESET_TTC2 = 1046, |
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ZYNQMP_PM_RESET_TTC3 = 1047, |
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ZYNQMP_PM_RESET_SWDT_CRL = 1048, |
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ZYNQMP_PM_RESET_NAND = 1049, |
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ZYNQMP_PM_RESET_ADMA = 1050, |
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ZYNQMP_PM_RESET_GPIO = 1051, |
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ZYNQMP_PM_RESET_IOU_CC = 1052, |
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ZYNQMP_PM_RESET_TIMESTAMP = 1053, |
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ZYNQMP_PM_RESET_RPU_R50 = 1054, |
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ZYNQMP_PM_RESET_RPU_R51 = 1055, |
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ZYNQMP_PM_RESET_RPU_AMBA = 1056, |
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ZYNQMP_PM_RESET_OCM = 1057, |
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ZYNQMP_PM_RESET_RPU_PGE = 1058, |
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ZYNQMP_PM_RESET_USB0_CORERESET = 1059, |
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ZYNQMP_PM_RESET_USB1_CORERESET = 1060, |
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ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, |
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ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, |
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ZYNQMP_PM_RESET_USB0_APB = 1063, |
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ZYNQMP_PM_RESET_USB1_APB = 1064, |
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ZYNQMP_PM_RESET_IPI = 1065, |
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ZYNQMP_PM_RESET_APM_LPD = 1066, |
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ZYNQMP_PM_RESET_RTC = 1067, |
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ZYNQMP_PM_RESET_SYSMON = 1068, |
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ZYNQMP_PM_RESET_AFI_FM6 = 1069, |
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ZYNQMP_PM_RESET_LPD_SWDT = 1070, |
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ZYNQMP_PM_RESET_FPD = 1071, |
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ZYNQMP_PM_RESET_RPU_DBG1 = 1072, |
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ZYNQMP_PM_RESET_RPU_DBG0 = 1073, |
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ZYNQMP_PM_RESET_DBG_LPD = 1074, |
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ZYNQMP_PM_RESET_DBG_FPD = 1075, |
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ZYNQMP_PM_RESET_APLL = 1076, |
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ZYNQMP_PM_RESET_DPLL = 1077, |
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ZYNQMP_PM_RESET_VPLL = 1078, |
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ZYNQMP_PM_RESET_IOPLL = 1079, |
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ZYNQMP_PM_RESET_RPLL = 1080, |
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ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, |
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ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, |
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ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, |
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ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, |
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ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, |
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ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, |
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ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, |
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ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, |
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ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, |
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ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, |
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ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, |
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ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, |
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ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, |
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ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, |
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ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, |
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ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, |
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ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, |
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ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, |
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ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, |
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ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, |
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ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, |
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ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, |
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ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, |
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ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, |
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ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, |
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ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, |
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ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, |
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ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, |
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ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, |
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ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, |
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ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, |
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ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, |
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ZYNQMP_PM_RESET_RPU_LS = 1113, |
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ZYNQMP_PM_RESET_PS_ONLY = 1114, |
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ZYNQMP_PM_RESET_PL = 1115, |
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ZYNQMP_PM_RESET_PS_PL0 = 1116, |
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ZYNQMP_PM_RESET_PS_PL1 = 1117, |
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ZYNQMP_PM_RESET_PS_PL2 = 1118, |
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ZYNQMP_PM_RESET_PS_PL3 = 1119, |
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ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 |
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}; |
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enum zynqmp_pm_suspend_reason { |
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SUSPEND_POWER_REQUEST = 201, |
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SUSPEND_ALERT = 202, |
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SUSPEND_SYSTEM_SHUTDOWN = 203, |
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}; |
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enum zynqmp_pm_request_ack { |
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ZYNQMP_PM_REQUEST_ACK_NO = 1, |
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ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2, |
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ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3, |
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}; |
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enum pm_node_id { |
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NODE_SD_0 = 39, |
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NODE_SD_1 = 40, |
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}; |
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enum tap_delay_type { |
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PM_TAPDELAY_INPUT = 0, |
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PM_TAPDELAY_OUTPUT = 1, |
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}; |
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enum dll_reset_type { |
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PM_DLL_RESET_ASSERT = 0, |
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PM_DLL_RESET_RELEASE = 1, |
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PM_DLL_RESET_PULSE = 2, |
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}; |
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enum zynqmp_pm_shutdown_type { |
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ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0, |
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ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1, |
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ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2, |
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}; |
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enum zynqmp_pm_shutdown_subtype { |
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ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0, |
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ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1, |
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ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2, |
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}; |
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/** |
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* struct zynqmp_pm_query_data - PM query data |
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* @qid: query ID |
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* @arg1: Argument 1 of query data |
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* @arg2: Argument 2 of query data |
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* @arg3: Argument 3 of query data |
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*/ |
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struct zynqmp_pm_query_data { |
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u32 qid; |
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u32 arg1; |
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u32 arg2; |
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u32 arg3; |
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}; |
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int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, |
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u32 arg2, u32 arg3, u32 *ret_payload); |
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#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) |
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int zynqmp_pm_get_api_version(u32 *version); |
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int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); |
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int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); |
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int zynqmp_pm_clock_enable(u32 clock_id); |
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int zynqmp_pm_clock_disable(u32 clock_id); |
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int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); |
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int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); |
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int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); |
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int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate); |
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int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate); |
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int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); |
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int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); |
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int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); |
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int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); |
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int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); |
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int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); |
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int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); |
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int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); |
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int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, |
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const enum zynqmp_pm_reset_action assert_flag); |
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int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); |
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int zynqmp_pm_init_finalize(void); |
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int zynqmp_pm_set_suspend_mode(u32 mode); |
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int zynqmp_pm_request_node(const u32 node, const u32 capabilities, |
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const u32 qos, const enum zynqmp_pm_request_ack ack); |
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int zynqmp_pm_release_node(const u32 node); |
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int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, |
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const u32 qos, |
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const enum zynqmp_pm_request_ack ack); |
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int zynqmp_pm_aes_engine(const u64 address, u32 *out); |
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int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); |
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int zynqmp_pm_fpga_get_status(u32 *value); |
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int zynqmp_pm_write_ggs(u32 index, u32 value); |
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int zynqmp_pm_read_ggs(u32 index, u32 *value); |
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int zynqmp_pm_write_pggs(u32 index, u32 value); |
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int zynqmp_pm_read_pggs(u32 index, u32 *value); |
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int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); |
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int zynqmp_pm_set_boot_health_status(u32 value); |
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#else |
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static inline int zynqmp_pm_get_api_version(u32 *version) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, |
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u32 *out) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_enable(u32 clock_id) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_disable(u32 clock_id) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) |
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{ |
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return -ENODEV; |
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} |
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static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, |
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const enum zynqmp_pm_reset_action assert_flag) |
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{ |
|
return -ENODEV; |
|
} |
|
|
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static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, |
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u32 *status) |
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{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_init_finalize(void) |
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{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_set_suspend_mode(u32 mode) |
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{ |
|
return -ENODEV; |
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} |
|
|
|
static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, |
|
const u32 qos, |
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const enum zynqmp_pm_request_ack ack) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_release_node(const u32 node) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_set_requirement(const u32 node, |
|
const u32 capabilities, |
|
const u32 qos, |
|
const enum zynqmp_pm_request_ack ack) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, |
|
const u32 flags) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_fpga_get_status(u32 *value) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_write_ggs(u32 index, u32 value) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_write_pggs(u32 index, u32 value) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) |
|
{ |
|
return -ENODEV; |
|
} |
|
|
|
static inline int zynqmp_pm_set_boot_health_status(u32 value) |
|
{ |
|
return -ENODEV; |
|
} |
|
#endif |
|
|
|
#endif /* __FIRMWARE_ZYNQMP_H__ */
|
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