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323 lines
12 KiB
323 lines
12 KiB
/* |
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* TI clock drivers support |
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* |
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* Copyright (C) 2013 Texas Instruments, Inc. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#ifndef __LINUX_CLK_TI_H__ |
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#define __LINUX_CLK_TI_H__ |
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#include <linux/clk-provider.h> |
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#include <linux/clkdev.h> |
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/** |
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* struct clk_omap_reg - OMAP register declaration |
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* @offset: offset from the master IP module base address |
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* @index: index of the master IP module |
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*/ |
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struct clk_omap_reg { |
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void __iomem *ptr; |
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u16 offset; |
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u8 index; |
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u8 flags; |
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}; |
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/** |
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* struct dpll_data - DPLL registers and integration data |
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* @mult_div1_reg: register containing the DPLL M and N bitfields |
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* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg |
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* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg |
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* @clk_bypass: struct clk_hw pointer to the clock's bypass clock input |
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* @clk_ref: struct clk_hw pointer to the clock's reference clock input |
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* @control_reg: register containing the DPLL mode bitfield |
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* @enable_mask: mask of the DPLL mode bitfield in @control_reg |
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* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() |
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* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() |
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* @last_rounded_m4xen: cache of the last M4X result of |
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* omap4_dpll_regm4xen_round_rate() |
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* @last_rounded_lpmode: cache of the last lpmode result of |
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* omap4_dpll_lpmode_recalc() |
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* @max_multiplier: maximum valid non-bypass multiplier value (actual) |
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* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() |
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* @min_divider: minimum valid non-bypass divider value (actual) |
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* @max_divider: maximum valid non-bypass divider value (actual) |
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* @max_rate: maximum clock rate for the DPLL |
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* @modes: possible values of @enable_mask |
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* @autoidle_reg: register containing the DPLL autoidle mode bitfield |
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* @idlest_reg: register containing the DPLL idle status bitfield |
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* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg |
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* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg |
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* @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg |
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* @dcc_rate: rate atleast which DCC @dcc_mask must be set |
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* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg |
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* @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg |
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* @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg |
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* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg |
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* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs |
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* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs |
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* @flags: DPLL type/features (see below) |
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* |
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* Possible values for @flags: |
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* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) |
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* |
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* @freqsel_mask is only used on the OMAP34xx family and AM35xx. |
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* |
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* XXX Some DPLLs have multiple bypass inputs, so it's not technically |
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* correct to only have one @clk_bypass pointer. |
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* |
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* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, |
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* @last_rounded_n) should be separated from the runtime-fixed fields |
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* and placed into a different structure, so that the runtime-fixed data |
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* can be placed into read-only space. |
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*/ |
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struct dpll_data { |
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struct clk_omap_reg mult_div1_reg; |
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u32 mult_mask; |
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u32 div1_mask; |
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struct clk_hw *clk_bypass; |
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struct clk_hw *clk_ref; |
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struct clk_omap_reg control_reg; |
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u32 enable_mask; |
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unsigned long last_rounded_rate; |
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u16 last_rounded_m; |
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u8 last_rounded_m4xen; |
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u8 last_rounded_lpmode; |
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u16 max_multiplier; |
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u8 last_rounded_n; |
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u8 min_divider; |
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u16 max_divider; |
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unsigned long max_rate; |
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u8 modes; |
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struct clk_omap_reg autoidle_reg; |
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struct clk_omap_reg idlest_reg; |
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u32 autoidle_mask; |
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u32 freqsel_mask; |
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u32 idlest_mask; |
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u32 dco_mask; |
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u32 sddiv_mask; |
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u32 dcc_mask; |
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unsigned long dcc_rate; |
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u32 lpmode_mask; |
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u32 m4xen_mask; |
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u8 auto_recal_bit; |
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u8 recal_en_bit; |
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u8 recal_st_bit; |
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u8 flags; |
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}; |
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struct clk_hw_omap; |
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/** |
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* struct clk_hw_omap_ops - OMAP clk ops |
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* @find_idlest: find idlest register information for a clock |
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* @find_companion: find companion clock register information for a clock, |
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* basically converts CM_ICLKEN* <-> CM_FCLKEN* |
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* @allow_idle: enables autoidle hardware functionality for a clock |
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* @deny_idle: prevent autoidle hardware functionality for a clock |
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*/ |
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struct clk_hw_omap_ops { |
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void (*find_idlest)(struct clk_hw_omap *oclk, |
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struct clk_omap_reg *idlest_reg, |
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u8 *idlest_bit, u8 *idlest_val); |
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void (*find_companion)(struct clk_hw_omap *oclk, |
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struct clk_omap_reg *other_reg, |
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u8 *other_bit); |
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void (*allow_idle)(struct clk_hw_omap *oclk); |
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void (*deny_idle)(struct clk_hw_omap *oclk); |
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}; |
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/** |
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* struct clk_hw_omap - OMAP struct clk |
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* @node: list_head connecting this clock into the full clock list |
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* @enable_reg: register to write to enable the clock (see @enable_bit) |
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* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) |
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* @flags: see "struct clk.flags possibilities" above |
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* @clksel_reg: for clksel clks, register va containing src/divisor select |
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* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock |
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* @clkdm_name: clockdomain name that this clock is contained in |
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* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime |
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* @ops: clock ops for this clock |
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*/ |
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struct clk_hw_omap { |
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struct clk_hw hw; |
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struct list_head node; |
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unsigned long fixed_rate; |
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u8 fixed_div; |
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struct clk_omap_reg enable_reg; |
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u8 enable_bit; |
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unsigned long flags; |
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struct clk_omap_reg clksel_reg; |
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struct dpll_data *dpll_data; |
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const char *clkdm_name; |
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struct clockdomain *clkdm; |
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const struct clk_hw_omap_ops *ops; |
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u32 context; |
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int autoidle_count; |
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}; |
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/* |
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* struct clk_hw_omap.flags possibilities |
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* |
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* XXX document the rest of the clock flags here |
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* |
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* ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed |
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* with 32bit ops, by default OMAP1 uses 16bit ops. |
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* CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support. |
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* CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent |
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* clock is put to no-idle mode. |
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* ENABLE_ON_INIT: Clock is enabled on init. |
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* INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0' |
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* disable. This inverts the behavior making '0' enable and '1' disable. |
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* CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL |
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* bits share the same register. This flag allows the |
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* omap4_dpllmx*() code to determine which GATE_CTRL bit field |
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* should be used. This is a temporary solution - a better approach |
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* would be to associate clock type-specific data with the clock, |
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* similar to the struct dpll_data approach. |
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*/ |
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#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ |
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#define CLOCK_IDLE_CONTROL (1 << 1) |
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#define CLOCK_NO_IDLE_PARENT (1 << 2) |
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#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ |
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#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ |
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#define CLOCK_CLKOUTX2 (1 << 5) |
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/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
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#define DPLL_LOW_POWER_STOP 0x1 |
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#define DPLL_LOW_POWER_BYPASS 0x5 |
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#define DPLL_LOCKED 0x7 |
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/* DPLL Type and DCO Selection Flags */ |
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#define DPLL_J_TYPE 0x1 |
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/* Static memmap indices */ |
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enum { |
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TI_CLKM_CM = 0, |
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TI_CLKM_CM2, |
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TI_CLKM_PRM, |
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TI_CLKM_SCRM, |
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TI_CLKM_CTRL, |
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TI_CLKM_CTRL_AUX, |
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TI_CLKM_PLLSS, |
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CLK_MAX_MEMMAPS |
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}; |
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/** |
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* struct ti_clk_ll_ops - low-level ops for clocks |
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* @clk_readl: pointer to register read function |
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* @clk_writel: pointer to register write function |
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* @clk_rmw: pointer to register read-modify-write function |
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* @clkdm_clk_enable: pointer to clockdomain enable function |
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* @clkdm_clk_disable: pointer to clockdomain disable function |
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* @clkdm_lookup: pointer to clockdomain lookup function |
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* @cm_wait_module_ready: pointer to CM module wait ready function |
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* @cm_split_idlest_reg: pointer to CM module function to split idlest reg |
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* |
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* Low-level ops are generally used by the basic clock types (clk-gate, |
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* clk-mux, clk-divider etc.) to provide support for various low-level |
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* hadrware interfaces (direct MMIO, regmap etc.), and is initialized |
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* by board code. Low-level ops also contain some other platform specific |
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* operations not provided directly by clock drivers. |
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*/ |
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struct ti_clk_ll_ops { |
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u32 (*clk_readl)(const struct clk_omap_reg *reg); |
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void (*clk_writel)(u32 val, const struct clk_omap_reg *reg); |
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void (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg); |
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int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk); |
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int (*clkdm_clk_disable)(struct clockdomain *clkdm, |
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struct clk *clk); |
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struct clockdomain * (*clkdm_lookup)(const char *name); |
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int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg, |
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u8 idlest_shift); |
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int (*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg, |
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s16 *prcm_inst, u8 *idlest_reg_id); |
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}; |
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#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) |
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bool omap2_clk_is_hw_omap(struct clk_hw *hw); |
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int omap2_clk_disable_autoidle_all(void); |
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int omap2_clk_enable_autoidle_all(void); |
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int omap2_clk_allow_idle(struct clk *clk); |
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int omap2_clk_deny_idle(struct clk *clk); |
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unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, |
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unsigned long parent_rate); |
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int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, |
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unsigned long parent_rate); |
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void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); |
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void omap2xxx_clkt_vps_init(void); |
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); |
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void ti_dt_clk_init_retry_clks(void); |
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void ti_dt_clockdomains_setup(void); |
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int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops); |
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struct regmap; |
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int omap2_clk_provider_init(struct device_node *parent, int index, |
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struct regmap *syscon, void __iomem *mem); |
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void omap2_clk_legacy_provider_init(int index, void __iomem *mem); |
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int omap3430_dt_clk_init(void); |
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int omap3630_dt_clk_init(void); |
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int am35xx_dt_clk_init(void); |
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int dm814x_dt_clk_init(void); |
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int dm816x_dt_clk_init(void); |
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int omap4xxx_dt_clk_init(void); |
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int omap5xxx_dt_clk_init(void); |
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int dra7xx_dt_clk_init(void); |
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int am33xx_dt_clk_init(void); |
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int am43xx_dt_clk_init(void); |
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int omap2420_dt_clk_init(void); |
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int omap2430_dt_clk_init(void); |
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struct ti_clk_features { |
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u32 flags; |
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long fint_min; |
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long fint_max; |
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long fint_band1_max; |
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long fint_band2_min; |
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u8 dpll_bypass_vals; |
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u8 cm_idlest_val; |
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}; |
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#define TI_CLK_DPLL_HAS_FREQSEL BIT(0) |
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#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) |
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#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) |
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#define TI_CLK_ERRATA_I810 BIT(3) |
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#define TI_CLK_CLKCTRL_COMPAT BIT(4) |
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#define TI_CLK_DEVICE_TYPE_GP BIT(5) |
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void ti_clk_setup_features(struct ti_clk_features *features); |
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const struct ti_clk_features *ti_clk_get_features(void); |
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bool ti_clk_is_in_standby(struct clk *clk); |
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int omap3_noncore_dpll_save_context(struct clk_hw *hw); |
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void omap3_noncore_dpll_restore_context(struct clk_hw *hw); |
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int omap3_core_dpll_save_context(struct clk_hw *hw); |
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void omap3_core_dpll_restore_context(struct clk_hw *hw); |
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extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; |
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#ifdef CONFIG_ATAGS |
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int omap3430_clk_legacy_init(void); |
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int omap3430es1_clk_legacy_init(void); |
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int omap36xx_clk_legacy_init(void); |
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int am35xx_clk_legacy_init(void); |
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#else |
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static inline int omap3430_clk_legacy_init(void) { return -ENXIO; } |
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static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; } |
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static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; } |
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static inline int am35xx_clk_legacy_init(void) { return -ENXIO; } |
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#endif |
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#endif
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