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73 lines
1.8 KiB
73 lines
1.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2006 Intel Corp. |
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* Tom Long Nguyen ([email protected]) |
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* Zhang Yanmin ([email protected]) |
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*/ |
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#ifndef _AER_H_ |
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#define _AER_H_ |
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#include <linux/errno.h> |
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#include <linux/types.h> |
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#define AER_NONFATAL 0 |
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#define AER_FATAL 1 |
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#define AER_CORRECTABLE 2 |
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#define DPC_FATAL 3 |
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struct pci_dev; |
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struct aer_header_log_regs { |
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unsigned int dw0; |
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unsigned int dw1; |
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unsigned int dw2; |
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unsigned int dw3; |
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}; |
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struct aer_capability_regs { |
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u32 header; |
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u32 uncor_status; |
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u32 uncor_mask; |
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u32 uncor_severity; |
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u32 cor_status; |
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u32 cor_mask; |
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u32 cap_control; |
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struct aer_header_log_regs header_log; |
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u32 root_command; |
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u32 root_status; |
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u16 cor_err_source; |
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u16 uncor_err_source; |
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}; |
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#if defined(CONFIG_PCIEAER) |
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/* PCIe port driver needs this function to enable AER */ |
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int pci_enable_pcie_error_reporting(struct pci_dev *dev); |
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int pci_disable_pcie_error_reporting(struct pci_dev *dev); |
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int pci_aer_clear_nonfatal_status(struct pci_dev *dev); |
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void pci_save_aer_state(struct pci_dev *dev); |
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void pci_restore_aer_state(struct pci_dev *dev); |
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#else |
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static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) |
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{ |
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return -EINVAL; |
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} |
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static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev) |
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{ |
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return -EINVAL; |
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} |
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static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) |
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{ |
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return -EINVAL; |
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} |
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static inline void pci_save_aer_state(struct pci_dev *dev) {} |
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static inline void pci_restore_aer_state(struct pci_dev *dev) {} |
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#endif |
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void cper_print_aer(struct pci_dev *dev, int aer_severity, |
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struct aer_capability_regs *aer); |
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int cper_severity_to_aer(int cper_severity); |
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void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, |
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int severity, struct aer_capability_regs *aer_regs); |
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#endif //_AER_H_ |
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