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76 lines
1.9 KiB
76 lines
1.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Qualcomm SDX55 interconnect IDs |
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* |
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* Copyright (c) 2021, Linaro Ltd. |
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* Author: Manivannan Sadhasivam <[email protected]> |
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*/ |
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H |
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX55_H |
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#define MASTER_LLCC 0 |
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#define SLAVE_EBI_CH0 1 |
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#define MASTER_TCU_0 0 |
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#define MASTER_SNOC_GC_MEM_NOC 1 |
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#define MASTER_AMPSS_M0 2 |
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#define SLAVE_LLCC 3 |
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#define SLAVE_MEM_NOC_SNOC 4 |
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#define SLAVE_MEM_NOC_PCIE_SNOC 5 |
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#define MASTER_AUDIO 0 |
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#define MASTER_BLSP_1 1 |
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#define MASTER_QDSS_BAM 2 |
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#define MASTER_QPIC 3 |
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#define MASTER_SNOC_CFG 4 |
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#define MASTER_SPMI_FETCHER 5 |
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#define MASTER_ANOC_SNOC 6 |
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#define MASTER_IPA 7 |
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#define MASTER_MEM_NOC_SNOC 8 |
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#define MASTER_MEM_NOC_PCIE_SNOC 9 |
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#define MASTER_CRYPTO_CORE_0 10 |
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#define MASTER_EMAC 11 |
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#define MASTER_IPA_PCIE 12 |
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#define MASTER_PCIE 13 |
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#define MASTER_QDSS_ETR 14 |
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#define MASTER_SDCC_1 15 |
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#define MASTER_USB3 16 |
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#define SLAVE_AOP 17 |
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#define SLAVE_AOSS 18 |
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#define SLAVE_APPSS 19 |
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#define SLAVE_AUDIO 20 |
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#define SLAVE_BLSP_1 21 |
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#define SLAVE_CLK_CTL 22 |
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#define SLAVE_CRYPTO_0_CFG 23 |
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#define SLAVE_CNOC_DDRSS 24 |
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#define SLAVE_ECC_CFG 25 |
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#define SLAVE_EMAC_CFG 26 |
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#define SLAVE_IMEM_CFG 27 |
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#define SLAVE_IPA_CFG 28 |
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#define SLAVE_CNOC_MSS 29 |
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#define SLAVE_PCIE_PARF 30 |
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#define SLAVE_PDM 31 |
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#define SLAVE_PRNG 32 |
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#define SLAVE_QDSS_CFG 33 |
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#define SLAVE_QPIC 34 |
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#define SLAVE_SDCC_1 35 |
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#define SLAVE_SNOC_CFG 36 |
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#define SLAVE_SPMI_FETCHER 37 |
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#define SLAVE_SPMI_VGI_COEX 38 |
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#define SLAVE_TCSR 39 |
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#define SLAVE_TLMM 40 |
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#define SLAVE_USB3 41 |
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#define SLAVE_USB3_PHY_CFG 42 |
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#define SLAVE_ANOC_SNOC 43 |
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#define SLAVE_SNOC_MEM_NOC_GC 44 |
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#define SLAVE_OCIMEM 45 |
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#define SLAVE_SERVICE_SNOC 46 |
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#define SLAVE_PCIE_0 47 |
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#define SLAVE_QDSS_STM 48 |
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#define SLAVE_TCU 49 |
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#define MASTER_IPA_CORE 0 |
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#define SLAVE_IPA_CORE 1 |
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#endif
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