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14 lines
504 B
14 lines
504 B
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ |
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H |
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H |
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/** @brief output of gate CLK_ENB_FUSE */ |
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#define TEGRA234_CLK_FUSE 40 |
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ |
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#define TEGRA234_CLK_SDMMC4 123 |
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ |
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#define TEGRA234_CLK_UARTA 155 |
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#endif
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