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152 lines
4.5 KiB
152 lines
4.5 KiB
/* |
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* Copyright (C) 2016 Maxime Ripard <[email protected]> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ |
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#define _DT_BINDINGS_CLK_SUN8I_H3_H_ |
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#define CLK_PLL_VIDEO 6 |
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#define CLK_PLL_PERIPH0 9 |
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#define CLK_CPUX 14 |
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#define CLK_BUS_CE 20 |
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#define CLK_BUS_DMA 21 |
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#define CLK_BUS_MMC0 22 |
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#define CLK_BUS_MMC1 23 |
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#define CLK_BUS_MMC2 24 |
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#define CLK_BUS_NAND 25 |
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#define CLK_BUS_DRAM 26 |
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#define CLK_BUS_EMAC 27 |
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#define CLK_BUS_TS 28 |
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#define CLK_BUS_HSTIMER 29 |
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#define CLK_BUS_SPI0 30 |
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#define CLK_BUS_SPI1 31 |
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#define CLK_BUS_OTG 32 |
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#define CLK_BUS_EHCI0 33 |
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#define CLK_BUS_EHCI1 34 |
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#define CLK_BUS_EHCI2 35 |
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#define CLK_BUS_EHCI3 36 |
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#define CLK_BUS_OHCI0 37 |
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#define CLK_BUS_OHCI1 38 |
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#define CLK_BUS_OHCI2 39 |
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#define CLK_BUS_OHCI3 40 |
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#define CLK_BUS_VE 41 |
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#define CLK_BUS_TCON0 42 |
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#define CLK_BUS_TCON1 43 |
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#define CLK_BUS_DEINTERLACE 44 |
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#define CLK_BUS_CSI 45 |
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#define CLK_BUS_TVE 46 |
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#define CLK_BUS_HDMI 47 |
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#define CLK_BUS_DE 48 |
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#define CLK_BUS_GPU 49 |
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#define CLK_BUS_MSGBOX 50 |
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#define CLK_BUS_SPINLOCK 51 |
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#define CLK_BUS_CODEC 52 |
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#define CLK_BUS_SPDIF 53 |
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#define CLK_BUS_PIO 54 |
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#define CLK_BUS_THS 55 |
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#define CLK_BUS_I2S0 56 |
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#define CLK_BUS_I2S1 57 |
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#define CLK_BUS_I2S2 58 |
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#define CLK_BUS_I2C0 59 |
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#define CLK_BUS_I2C1 60 |
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#define CLK_BUS_I2C2 61 |
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#define CLK_BUS_UART0 62 |
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#define CLK_BUS_UART1 63 |
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#define CLK_BUS_UART2 64 |
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#define CLK_BUS_UART3 65 |
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#define CLK_BUS_SCR0 66 |
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#define CLK_BUS_EPHY 67 |
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#define CLK_BUS_DBG 68 |
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#define CLK_THS 69 |
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#define CLK_NAND 70 |
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#define CLK_MMC0 71 |
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#define CLK_MMC0_SAMPLE 72 |
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#define CLK_MMC0_OUTPUT 73 |
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#define CLK_MMC1 74 |
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#define CLK_MMC1_SAMPLE 75 |
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#define CLK_MMC1_OUTPUT 76 |
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#define CLK_MMC2 77 |
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#define CLK_MMC2_SAMPLE 78 |
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#define CLK_MMC2_OUTPUT 79 |
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#define CLK_TS 80 |
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#define CLK_CE 81 |
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#define CLK_SPI0 82 |
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#define CLK_SPI1 83 |
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#define CLK_I2S0 84 |
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#define CLK_I2S1 85 |
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#define CLK_I2S2 86 |
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#define CLK_SPDIF 87 |
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#define CLK_USB_PHY0 88 |
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#define CLK_USB_PHY1 89 |
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#define CLK_USB_PHY2 90 |
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#define CLK_USB_PHY3 91 |
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#define CLK_USB_OHCI0 92 |
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#define CLK_USB_OHCI1 93 |
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#define CLK_USB_OHCI2 94 |
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#define CLK_USB_OHCI3 95 |
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#define CLK_DRAM_VE 97 |
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#define CLK_DRAM_CSI 98 |
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#define CLK_DRAM_DEINTERLACE 99 |
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#define CLK_DRAM_TS 100 |
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#define CLK_DE 101 |
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#define CLK_TCON0 102 |
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#define CLK_TVE 103 |
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#define CLK_DEINTERLACE 104 |
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#define CLK_CSI_MISC 105 |
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#define CLK_CSI_SCLK 106 |
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#define CLK_CSI_MCLK 107 |
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#define CLK_VE 108 |
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#define CLK_AC_DIG 109 |
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#define CLK_AVS 110 |
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#define CLK_HDMI 111 |
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#define CLK_HDMI_DDC 112 |
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#define CLK_MBUS 113 |
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#define CLK_GPU 114 |
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/* New clocks imported in H5 */ |
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#define CLK_BUS_SCR1 115 |
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#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
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