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202 lines
5.6 KiB
202 lines
5.6 KiB
/* |
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* Copyright (C) 2017 Priit Laes <[email protected]> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ |
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#define _DT_BINDINGS_CLK_SUN4I_A10_H_ |
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#define CLK_HOSC 1 |
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#define CLK_PLL_VIDEO0_2X 9 |
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#define CLK_PLL_VIDEO1_2X 18 |
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#define CLK_CPU 20 |
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/* AHB Gates */ |
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#define CLK_AHB_OTG 26 |
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#define CLK_AHB_EHCI0 27 |
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#define CLK_AHB_OHCI0 28 |
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#define CLK_AHB_EHCI1 29 |
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#define CLK_AHB_OHCI1 30 |
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#define CLK_AHB_SS 31 |
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#define CLK_AHB_DMA 32 |
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#define CLK_AHB_BIST 33 |
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#define CLK_AHB_MMC0 34 |
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#define CLK_AHB_MMC1 35 |
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#define CLK_AHB_MMC2 36 |
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#define CLK_AHB_MMC3 37 |
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#define CLK_AHB_MS 38 |
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#define CLK_AHB_NAND 39 |
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#define CLK_AHB_SDRAM 40 |
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#define CLK_AHB_ACE 41 |
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#define CLK_AHB_EMAC 42 |
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#define CLK_AHB_TS 43 |
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#define CLK_AHB_SPI0 44 |
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#define CLK_AHB_SPI1 45 |
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#define CLK_AHB_SPI2 46 |
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#define CLK_AHB_SPI3 47 |
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#define CLK_AHB_PATA 48 |
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#define CLK_AHB_SATA 49 |
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#define CLK_AHB_GPS 50 |
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#define CLK_AHB_HSTIMER 51 |
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#define CLK_AHB_VE 52 |
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#define CLK_AHB_TVD 53 |
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#define CLK_AHB_TVE0 54 |
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#define CLK_AHB_TVE1 55 |
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#define CLK_AHB_LCD0 56 |
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#define CLK_AHB_LCD1 57 |
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#define CLK_AHB_CSI0 58 |
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#define CLK_AHB_CSI1 59 |
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#define CLK_AHB_HDMI0 60 |
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#define CLK_AHB_HDMI1 61 |
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#define CLK_AHB_DE_BE0 62 |
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#define CLK_AHB_DE_BE1 63 |
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#define CLK_AHB_DE_FE0 64 |
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#define CLK_AHB_DE_FE1 65 |
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#define CLK_AHB_GMAC 66 |
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#define CLK_AHB_MP 67 |
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#define CLK_AHB_GPU 68 |
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/* APB0 Gates */ |
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#define CLK_APB0_CODEC 69 |
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#define CLK_APB0_SPDIF 70 |
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#define CLK_APB0_I2S0 71 |
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#define CLK_APB0_AC97 72 |
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#define CLK_APB0_I2S1 73 |
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#define CLK_APB0_PIO 74 |
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#define CLK_APB0_IR0 75 |
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#define CLK_APB0_IR1 76 |
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#define CLK_APB0_I2S2 77 |
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#define CLK_APB0_KEYPAD 78 |
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/* APB1 Gates */ |
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#define CLK_APB1_I2C0 79 |
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#define CLK_APB1_I2C1 80 |
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#define CLK_APB1_I2C2 81 |
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#define CLK_APB1_I2C3 82 |
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#define CLK_APB1_CAN 83 |
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#define CLK_APB1_SCR 84 |
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#define CLK_APB1_PS20 85 |
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#define CLK_APB1_PS21 86 |
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#define CLK_APB1_I2C4 87 |
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#define CLK_APB1_UART0 88 |
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#define CLK_APB1_UART1 89 |
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#define CLK_APB1_UART2 90 |
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#define CLK_APB1_UART3 91 |
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#define CLK_APB1_UART4 92 |
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#define CLK_APB1_UART5 93 |
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#define CLK_APB1_UART6 94 |
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#define CLK_APB1_UART7 95 |
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/* IP clocks */ |
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#define CLK_NAND 96 |
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#define CLK_MS 97 |
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#define CLK_MMC0 98 |
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#define CLK_MMC0_OUTPUT 99 |
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#define CLK_MMC0_SAMPLE 100 |
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#define CLK_MMC1 101 |
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#define CLK_MMC1_OUTPUT 102 |
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#define CLK_MMC1_SAMPLE 103 |
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#define CLK_MMC2 104 |
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#define CLK_MMC2_OUTPUT 105 |
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#define CLK_MMC2_SAMPLE 106 |
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#define CLK_MMC3 107 |
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#define CLK_MMC3_OUTPUT 108 |
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#define CLK_MMC3_SAMPLE 109 |
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#define CLK_TS 110 |
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#define CLK_SS 111 |
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#define CLK_SPI0 112 |
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#define CLK_SPI1 113 |
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#define CLK_SPI2 114 |
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#define CLK_PATA 115 |
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#define CLK_IR0 116 |
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#define CLK_IR1 117 |
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#define CLK_I2S0 118 |
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#define CLK_AC97 119 |
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#define CLK_SPDIF 120 |
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#define CLK_KEYPAD 121 |
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#define CLK_SATA 122 |
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#define CLK_USB_OHCI0 123 |
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#define CLK_USB_OHCI1 124 |
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#define CLK_USB_PHY 125 |
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#define CLK_GPS 126 |
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#define CLK_SPI3 127 |
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#define CLK_I2S1 128 |
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#define CLK_I2S2 129 |
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/* DRAM Gates */ |
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#define CLK_DRAM_VE 130 |
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#define CLK_DRAM_CSI0 131 |
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#define CLK_DRAM_CSI1 132 |
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#define CLK_DRAM_TS 133 |
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#define CLK_DRAM_TVD 134 |
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#define CLK_DRAM_TVE0 135 |
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#define CLK_DRAM_TVE1 136 |
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#define CLK_DRAM_OUT 137 |
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#define CLK_DRAM_DE_FE1 138 |
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#define CLK_DRAM_DE_FE0 139 |
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#define CLK_DRAM_DE_BE0 140 |
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#define CLK_DRAM_DE_BE1 141 |
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#define CLK_DRAM_MP 142 |
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#define CLK_DRAM_ACE 143 |
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/* Display Engine Clocks */ |
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#define CLK_DE_BE0 144 |
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#define CLK_DE_BE1 145 |
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#define CLK_DE_FE0 146 |
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#define CLK_DE_FE1 147 |
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#define CLK_DE_MP 148 |
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#define CLK_TCON0_CH0 149 |
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#define CLK_TCON1_CH0 150 |
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#define CLK_CSI_SCLK 151 |
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#define CLK_TVD_SCLK2 152 |
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#define CLK_TVD 153 |
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#define CLK_TCON0_CH1_SCLK2 154 |
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#define CLK_TCON0_CH1 155 |
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#define CLK_TCON1_CH1_SCLK2 156 |
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#define CLK_TCON1_CH1 157 |
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#define CLK_CSI0 158 |
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#define CLK_CSI1 159 |
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#define CLK_CODEC 160 |
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#define CLK_VE 161 |
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#define CLK_AVS 162 |
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#define CLK_ACE 163 |
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#define CLK_HDMI 164 |
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#define CLK_GPU 165 |
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#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
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