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165 lines
3.1 KiB
165 lines
3.1 KiB
/* SYS, CORE AND BUS CLOCKS */ |
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#define SYS_D1CPRE 0 |
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#define HCLK 1 |
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#define PCLK1 2 |
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#define PCLK2 3 |
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#define PCLK3 4 |
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#define PCLK4 5 |
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#define HSI_DIV 6 |
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#define HSE_1M 7 |
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#define I2S_CKIN 8 |
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#define CK_DSI_PHY 9 |
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#define HSE_CK 10 |
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#define LSE_CK 11 |
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#define CSI_KER_DIV122 12 |
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#define RTC_CK 13 |
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#define CPU_SYSTICK 14 |
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/* OSCILLATOR BANK */ |
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#define OSC_BANK 18 |
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#define HSI_CK 18 |
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#define HSI_KER_CK 19 |
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#define CSI_CK 20 |
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#define CSI_KER_CK 21 |
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#define RC48_CK 22 |
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#define LSI_CK 23 |
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/* MCLOCK BANK */ |
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#define MCLK_BANK 28 |
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#define PER_CK 28 |
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#define PLLSRC 29 |
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#define SYS_CK 30 |
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#define TRACEIN_CK 31 |
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/* ODF BANK */ |
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#define ODF_BANK 32 |
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#define PLL1_P 32 |
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#define PLL1_Q 33 |
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#define PLL1_R 34 |
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#define PLL2_P 35 |
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#define PLL2_Q 36 |
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#define PLL2_R 37 |
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#define PLL3_P 38 |
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#define PLL3_Q 39 |
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#define PLL3_R 40 |
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/* MCO BANK */ |
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#define MCO_BANK 41 |
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#define MCO1 41 |
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#define MCO2 42 |
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/* PERIF BANK */ |
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#define PERIF_BANK 50 |
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#define D1SRAM1_CK 50 |
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#define ITCM_CK 51 |
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#define DTCM2_CK 52 |
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#define DTCM1_CK 53 |
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#define FLITF_CK 54 |
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#define JPGDEC_CK 55 |
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#define DMA2D_CK 56 |
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#define MDMA_CK 57 |
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#define USB2ULPI_CK 58 |
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#define USB1ULPI_CK 59 |
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#define ETH1RX_CK 60 |
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#define ETH1TX_CK 61 |
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#define ETH1MAC_CK 62 |
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#define ART_CK 63 |
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#define DMA2_CK 64 |
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#define DMA1_CK 65 |
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#define D2SRAM3_CK 66 |
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#define D2SRAM2_CK 67 |
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#define D2SRAM1_CK 68 |
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#define HASH_CK 69 |
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#define CRYPT_CK 70 |
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#define CAMITF_CK 71 |
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#define BKPRAM_CK 72 |
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#define HSEM_CK 73 |
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#define BDMA_CK 74 |
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#define CRC_CK 75 |
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#define GPIOK_CK 76 |
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#define GPIOJ_CK 77 |
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#define GPIOI_CK 78 |
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#define GPIOH_CK 79 |
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#define GPIOG_CK 80 |
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#define GPIOF_CK 81 |
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#define GPIOE_CK 82 |
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#define GPIOD_CK 83 |
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#define GPIOC_CK 84 |
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#define GPIOB_CK 85 |
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#define GPIOA_CK 86 |
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#define WWDG1_CK 87 |
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#define DAC12_CK 88 |
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#define WWDG2_CK 89 |
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#define TIM14_CK 90 |
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#define TIM13_CK 91 |
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#define TIM12_CK 92 |
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#define TIM7_CK 93 |
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#define TIM6_CK 94 |
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#define TIM5_CK 95 |
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#define TIM4_CK 96 |
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#define TIM3_CK 97 |
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#define TIM2_CK 98 |
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#define MDIOS_CK 99 |
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#define OPAMP_CK 100 |
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#define CRS_CK 101 |
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#define TIM17_CK 102 |
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#define TIM16_CK 103 |
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#define TIM15_CK 104 |
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#define TIM8_CK 105 |
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#define TIM1_CK 106 |
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#define TMPSENS_CK 107 |
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#define RTCAPB_CK 108 |
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#define VREF_CK 109 |
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#define COMP12_CK 110 |
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#define SYSCFG_CK 111 |
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/* KERNEL BANK */ |
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#define KERN_BANK 120 |
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#define SDMMC1_CK 120 |
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#define QUADSPI_CK 121 |
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#define FMC_CK 122 |
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#define USB2OTG_CK 123 |
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#define USB1OTG_CK 124 |
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#define ADC12_CK 125 |
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#define SDMMC2_CK 126 |
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#define RNG_CK 127 |
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#define ADC3_CK 128 |
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#define DSI_CK 129 |
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#define LTDC_CK 130 |
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#define USART8_CK 131 |
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#define USART7_CK 132 |
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#define HDMICEC_CK 133 |
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#define I2C3_CK 134 |
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#define I2C2_CK 135 |
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#define I2C1_CK 136 |
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#define UART5_CK 137 |
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#define UART4_CK 138 |
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#define USART3_CK 139 |
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#define USART2_CK 140 |
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#define SPDIFRX_CK 141 |
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#define SPI3_CK 142 |
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#define SPI2_CK 143 |
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#define LPTIM1_CK 144 |
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#define FDCAN_CK 145 |
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#define SWP_CK 146 |
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#define HRTIM_CK 147 |
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#define DFSDM1_CK 148 |
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#define SAI3_CK 149 |
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#define SAI2_CK 150 |
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#define SAI1_CK 151 |
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#define SPI5_CK 152 |
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#define SPI4_CK 153 |
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#define SPI1_CK 154 |
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#define USART6_CK 155 |
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#define USART1_CK 156 |
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#define SAI4B_CK 157 |
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#define SAI4A_CK 158 |
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#define LPTIM5_CK 159 |
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#define LPTIM4_CK 160 |
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#define LPTIM3_CK 161 |
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#define LPTIM2_CK 162 |
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#define I2C4_CK 163 |
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#define SPI6_CK 164 |
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#define LPUART1_CK 165 |
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#define STM32H7_MAX_CLKS 166
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