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321 lines
8.9 KiB
321 lines
8.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
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* Copyright (c) BayLibre, SAS. |
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* Author : Neil Armstrong <[email protected]> |
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*/ |
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#ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H |
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#define _DT_BINDINGS_CLK_MDM_GCC_9615_H |
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#define AFAB_CLK_SRC 0 |
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#define AFAB_CORE_CLK 1 |
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#define SFAB_MSS_Q6_SW_A_CLK 2 |
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#define SFAB_MSS_Q6_FW_A_CLK 3 |
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#define QDSS_STM_CLK 4 |
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#define SCSS_A_CLK 5 |
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#define SCSS_H_CLK 6 |
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#define SCSS_XO_SRC_CLK 7 |
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#define AFAB_EBI1_CH0_A_CLK 8 |
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#define AFAB_EBI1_CH1_A_CLK 9 |
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#define AFAB_AXI_S0_FCLK 10 |
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#define AFAB_AXI_S1_FCLK 11 |
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#define AFAB_AXI_S2_FCLK 12 |
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#define AFAB_AXI_S3_FCLK 13 |
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#define AFAB_AXI_S4_FCLK 14 |
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#define SFAB_CORE_CLK 15 |
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#define SFAB_AXI_S0_FCLK 16 |
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#define SFAB_AXI_S1_FCLK 17 |
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#define SFAB_AXI_S2_FCLK 18 |
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#define SFAB_AXI_S3_FCLK 19 |
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#define SFAB_AXI_S4_FCLK 20 |
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#define SFAB_AHB_S0_FCLK 21 |
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#define SFAB_AHB_S1_FCLK 22 |
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#define SFAB_AHB_S2_FCLK 23 |
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#define SFAB_AHB_S3_FCLK 24 |
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#define SFAB_AHB_S4_FCLK 25 |
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#define SFAB_AHB_S5_FCLK 26 |
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#define SFAB_AHB_S6_FCLK 27 |
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#define SFAB_AHB_S7_FCLK 28 |
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#define QDSS_AT_CLK_SRC 29 |
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#define QDSS_AT_CLK 30 |
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#define QDSS_TRACECLKIN_CLK_SRC 31 |
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#define QDSS_TRACECLKIN_CLK 32 |
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#define QDSS_TSCTR_CLK_SRC 33 |
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#define QDSS_TSCTR_CLK 34 |
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#define SFAB_ADM0_M0_A_CLK 35 |
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#define SFAB_ADM0_M1_A_CLK 36 |
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#define SFAB_ADM0_M2_H_CLK 37 |
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#define ADM0_CLK 38 |
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#define ADM0_PBUS_CLK 39 |
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#define MSS_XPU_CLK 40 |
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#define IMEM0_A_CLK 41 |
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#define QDSS_H_CLK 42 |
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#define PCIE_A_CLK 43 |
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#define PCIE_AUX_CLK 44 |
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#define PCIE_PHY_REF_CLK 45 |
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#define PCIE_H_CLK 46 |
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#define SFAB_CLK_SRC 47 |
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#define MAHB0_CLK 48 |
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#define Q6SW_CLK_SRC 49 |
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#define Q6SW_CLK 50 |
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#define Q6FW_CLK_SRC 51 |
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#define Q6FW_CLK 52 |
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#define SFAB_MSS_M_A_CLK 53 |
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#define SFAB_USB3_M_A_CLK 54 |
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#define SFAB_LPASS_Q6_A_CLK 55 |
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#define SFAB_AFAB_M_A_CLK 56 |
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#define AFAB_SFAB_M0_A_CLK 57 |
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#define AFAB_SFAB_M1_A_CLK 58 |
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#define SFAB_SATA_S_H_CLK 59 |
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#define DFAB_CLK_SRC 60 |
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#define DFAB_CLK 61 |
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#define SFAB_DFAB_M_A_CLK 62 |
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#define DFAB_SFAB_M_A_CLK 63 |
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#define DFAB_SWAY0_H_CLK 64 |
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#define DFAB_SWAY1_H_CLK 65 |
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#define DFAB_ARB0_H_CLK 66 |
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#define DFAB_ARB1_H_CLK 67 |
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#define PPSS_H_CLK 68 |
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#define PPSS_PROC_CLK 69 |
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#define PPSS_TIMER0_CLK 70 |
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#define PPSS_TIMER1_CLK 71 |
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#define PMEM_A_CLK 72 |
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#define DMA_BAM_H_CLK 73 |
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#define SIC_H_CLK 74 |
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#define SPS_TIC_H_CLK 75 |
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#define SLIMBUS_H_CLK 76 |
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#define SLIMBUS_XO_SRC_CLK 77 |
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#define CFPB_2X_CLK_SRC 78 |
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#define CFPB_CLK 79 |
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#define CFPB0_H_CLK 80 |
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#define CFPB1_H_CLK 81 |
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#define CFPB2_H_CLK 82 |
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#define SFAB_CFPB_M_H_CLK 83 |
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#define CFPB_MASTER_H_CLK 84 |
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#define SFAB_CFPB_S_H_CLK 85 |
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#define CFPB_SPLITTER_H_CLK 86 |
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#define TSIF_H_CLK 87 |
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#define TSIF_INACTIVITY_TIMERS_CLK 88 |
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#define TSIF_REF_SRC 89 |
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#define TSIF_REF_CLK 90 |
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#define CE1_H_CLK 91 |
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#define CE1_CORE_CLK 92 |
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#define CE1_SLEEP_CLK 93 |
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#define CE2_H_CLK 94 |
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#define CE2_CORE_CLK 95 |
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#define SFPB_H_CLK_SRC 97 |
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#define SFPB_H_CLK 98 |
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#define SFAB_SFPB_M_H_CLK 99 |
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#define SFAB_SFPB_S_H_CLK 100 |
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#define RPM_PROC_CLK 101 |
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#define RPM_BUS_H_CLK 102 |
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#define RPM_SLEEP_CLK 103 |
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#define RPM_TIMER_CLK 104 |
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#define RPM_MSG_RAM_H_CLK 105 |
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#define PMIC_ARB0_H_CLK 106 |
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#define PMIC_ARB1_H_CLK 107 |
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#define PMIC_SSBI2_SRC 108 |
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#define PMIC_SSBI2_CLK 109 |
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#define SDC1_H_CLK 110 |
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#define SDC2_H_CLK 111 |
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#define SDC3_H_CLK 112 |
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#define SDC4_H_CLK 113 |
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#define SDC5_H_CLK 114 |
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#define SDC1_SRC 115 |
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#define SDC2_SRC 116 |
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#define SDC3_SRC 117 |
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#define SDC4_SRC 118 |
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#define SDC5_SRC 119 |
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#define SDC1_CLK 120 |
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#define SDC2_CLK 121 |
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#define SDC3_CLK 122 |
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#define SDC4_CLK 123 |
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#define SDC5_CLK 124 |
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#define DFAB_A2_H_CLK 125 |
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#define USB_HS1_H_CLK 126 |
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#define USB_HS1_XCVR_SRC 127 |
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#define USB_HS1_XCVR_CLK 128 |
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#define USB_HSIC_H_CLK 129 |
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#define USB_HSIC_XCVR_FS_SRC 130 |
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#define USB_HSIC_XCVR_FS_CLK 131 |
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#define USB_HSIC_SYSTEM_CLK_SRC 132 |
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#define USB_HSIC_SYSTEM_CLK 133 |
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#define CFPB0_C0_H_CLK 134 |
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#define CFPB0_C1_H_CLK 135 |
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#define CFPB0_D0_H_CLK 136 |
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#define CFPB0_D1_H_CLK 137 |
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#define USB_FS1_H_CLK 138 |
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#define USB_FS1_XCVR_FS_SRC 139 |
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#define USB_FS1_XCVR_FS_CLK 140 |
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#define USB_FS1_SYSTEM_CLK 141 |
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#define USB_FS2_H_CLK 142 |
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#define USB_FS2_XCVR_FS_SRC 143 |
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#define USB_FS2_XCVR_FS_CLK 144 |
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#define USB_FS2_SYSTEM_CLK 145 |
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#define GSBI_COMMON_SIM_SRC 146 |
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#define GSBI1_H_CLK 147 |
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#define GSBI2_H_CLK 148 |
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#define GSBI3_H_CLK 149 |
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#define GSBI4_H_CLK 150 |
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#define GSBI5_H_CLK 151 |
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#define GSBI6_H_CLK 152 |
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#define GSBI7_H_CLK 153 |
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#define GSBI8_H_CLK 154 |
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#define GSBI9_H_CLK 155 |
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#define GSBI10_H_CLK 156 |
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#define GSBI11_H_CLK 157 |
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#define GSBI12_H_CLK 158 |
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#define GSBI1_UART_SRC 159 |
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#define GSBI1_UART_CLK 160 |
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#define GSBI2_UART_SRC 161 |
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#define GSBI2_UART_CLK 162 |
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#define GSBI3_UART_SRC 163 |
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#define GSBI3_UART_CLK 164 |
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#define GSBI4_UART_SRC 165 |
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#define GSBI4_UART_CLK 166 |
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#define GSBI5_UART_SRC 167 |
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#define GSBI5_UART_CLK 168 |
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#define GSBI6_UART_SRC 169 |
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#define GSBI6_UART_CLK 170 |
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#define GSBI7_UART_SRC 171 |
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#define GSBI7_UART_CLK 172 |
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#define GSBI8_UART_SRC 173 |
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#define GSBI8_UART_CLK 174 |
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#define GSBI9_UART_SRC 175 |
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#define GSBI9_UART_CLK 176 |
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#define GSBI10_UART_SRC 177 |
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#define GSBI10_UART_CLK 178 |
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#define GSBI11_UART_SRC 179 |
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#define GSBI11_UART_CLK 180 |
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#define GSBI12_UART_SRC 181 |
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#define GSBI12_UART_CLK 182 |
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#define GSBI1_QUP_SRC 183 |
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#define GSBI1_QUP_CLK 184 |
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#define GSBI2_QUP_SRC 185 |
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#define GSBI2_QUP_CLK 186 |
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#define GSBI3_QUP_SRC 187 |
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#define GSBI3_QUP_CLK 188 |
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#define GSBI4_QUP_SRC 189 |
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#define GSBI4_QUP_CLK 190 |
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#define GSBI5_QUP_SRC 191 |
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#define GSBI5_QUP_CLK 192 |
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#define GSBI6_QUP_SRC 193 |
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#define GSBI6_QUP_CLK 194 |
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#define GSBI7_QUP_SRC 195 |
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#define GSBI7_QUP_CLK 196 |
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#define GSBI8_QUP_SRC 197 |
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#define GSBI8_QUP_CLK 198 |
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#define GSBI9_QUP_SRC 199 |
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#define GSBI9_QUP_CLK 200 |
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#define GSBI10_QUP_SRC 201 |
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#define GSBI10_QUP_CLK 202 |
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#define GSBI11_QUP_SRC 203 |
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#define GSBI11_QUP_CLK 204 |
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#define GSBI12_QUP_SRC 205 |
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#define GSBI12_QUP_CLK 206 |
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#define GSBI1_SIM_CLK 207 |
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#define GSBI2_SIM_CLK 208 |
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#define GSBI3_SIM_CLK 209 |
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#define GSBI4_SIM_CLK 210 |
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#define GSBI5_SIM_CLK 211 |
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#define GSBI6_SIM_CLK 212 |
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#define GSBI7_SIM_CLK 213 |
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#define GSBI8_SIM_CLK 214 |
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#define GSBI9_SIM_CLK 215 |
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#define GSBI10_SIM_CLK 216 |
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#define GSBI11_SIM_CLK 217 |
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#define GSBI12_SIM_CLK 218 |
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#define USB_HSIC_HSIC_CLK_SRC 219 |
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#define USB_HSIC_HSIC_CLK 220 |
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#define USB_HSIC_HSIO_CAL_CLK 221 |
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#define SPDM_CFG_H_CLK 222 |
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#define SPDM_MSTR_H_CLK 223 |
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#define SPDM_FF_CLK_SRC 224 |
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#define SPDM_FF_CLK 225 |
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#define SEC_CTRL_CLK 226 |
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#define SEC_CTRL_ACC_CLK_SRC 227 |
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#define SEC_CTRL_ACC_CLK 228 |
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#define TLMM_H_CLK 229 |
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#define TLMM_CLK 230 |
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#define SFAB_MSS_S_H_CLK 231 |
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#define MSS_SLP_CLK 232 |
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#define MSS_Q6SW_JTAG_CLK 233 |
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#define MSS_Q6FW_JTAG_CLK 234 |
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#define MSS_S_H_CLK 235 |
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#define MSS_CXO_SRC_CLK 236 |
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#define SATA_H_CLK 237 |
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#define SATA_CLK_SRC 238 |
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#define SATA_RXOOB_CLK 239 |
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#define SATA_PMALIVE_CLK 240 |
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#define SATA_PHY_REF_CLK 241 |
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#define TSSC_CLK_SRC 242 |
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#define TSSC_CLK 243 |
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#define PDM_SRC 244 |
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#define PDM_CLK 245 |
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#define GP0_SRC 246 |
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#define GP0_CLK 247 |
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#define GP1_SRC 248 |
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#define GP1_CLK 249 |
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#define GP2_SRC 250 |
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#define GP2_CLK 251 |
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#define MPM_CLK 252 |
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#define EBI1_CLK_SRC 253 |
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#define EBI1_CH0_CLK 254 |
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#define EBI1_CH1_CLK 255 |
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#define EBI1_2X_CLK 256 |
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#define EBI1_CH0_DQ_CLK 257 |
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#define EBI1_CH1_DQ_CLK 258 |
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#define EBI1_CH0_CA_CLK 259 |
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#define EBI1_CH1_CA_CLK 260 |
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#define EBI1_XO_CLK 261 |
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#define SFAB_SMPSS_S_H_CLK 262 |
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#define PRNG_SRC 263 |
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#define PRNG_CLK 264 |
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#define PXO_SRC 265 |
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#define LPASS_CXO_CLK 266 |
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#define LPASS_PXO_CLK 267 |
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#define SPDM_CY_PORT0_CLK 268 |
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#define SPDM_CY_PORT1_CLK 269 |
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#define SPDM_CY_PORT2_CLK 270 |
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#define SPDM_CY_PORT3_CLK 271 |
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#define SPDM_CY_PORT4_CLK 272 |
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#define SPDM_CY_PORT5_CLK 273 |
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#define SPDM_CY_PORT6_CLK 274 |
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#define SPDM_CY_PORT7_CLK 275 |
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#define PLL0 276 |
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#define PLL0_VOTE 277 |
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#define PLL3 278 |
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#define PLL3_VOTE 279 |
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#define PLL4_VOTE 280 |
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#define PLL5 281 |
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#define PLL5_VOTE 282 |
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#define PLL6 283 |
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#define PLL6_VOTE 284 |
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#define PLL7_VOTE 285 |
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#define PLL8 286 |
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#define PLL8_VOTE 287 |
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#define PLL9 288 |
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#define PLL10 289 |
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#define PLL11 290 |
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#define PLL12 291 |
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#define PLL13 292 |
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#define PLL14 293 |
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#define PLL14_VOTE 294 |
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#define USB_HS3_H_CLK 295 |
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#define USB_HS3_XCVR_SRC 296 |
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#define USB_HS3_XCVR_CLK 297 |
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#define USB_HS4_H_CLK 298 |
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#define USB_HS4_XCVR_SRC 299 |
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#define USB_HS4_XCVR_CLK 300 |
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#define SATA_PHY_CFG_CLK 301 |
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#define SATA_A_CLK 302 |
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#define CE3_SRC 303 |
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#define CE3_CORE_CLK 304 |
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#define CE3_H_CLK 305 |
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#define USB_HS1_SYSTEM_CLK_SRC 306 |
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#define USB_HS1_SYSTEM_CLK 307 |
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#define EBI2_CLK 308 |
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#define EBI2_AON_CLK 309 |
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#endif
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