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51 lines
2.1 KiB
51 lines
2.1 KiB
/* |
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* BSD LICENSE |
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* |
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* Copyright(c) 2015 Broadcom Corporation. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* * Neither the name of Broadcom Corporation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef _CLOCK_BCM_NSP_H |
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#define _CLOCK_BCM_NSP_H |
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/* GENPLL clock channel ID */ |
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#define BCM_NSP_GENPLL 0 |
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#define BCM_NSP_GENPLL_PHY_CLK 1 |
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#define BCM_NSP_GENPLL_ENET_SW_CLK 2 |
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#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 |
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#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 |
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#define BCM_NSP_GENPLL_SATA1_CLK 5 |
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#define BCM_NSP_GENPLL_SATA2_CLK 6 |
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/* LCPLL0 clock channel ID */ |
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#define BCM_NSP_LCPLL0 0 |
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#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 |
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#define BCM_NSP_LCPLL0_SDIO_CLK 2 |
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#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 |
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#endif /* _CLOCK_BCM_NSP_H */
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