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547 lines
17 KiB
547 lines
17 KiB
/* |
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* Copyright © 2007-2008 Intel Corporation |
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* Jesse Barnes <[email protected]> |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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#ifndef __DRM_EDID_H__ |
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#define __DRM_EDID_H__ |
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#include <linux/types.h> |
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#include <linux/hdmi.h> |
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#include <drm/drm_mode.h> |
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struct drm_device; |
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struct i2c_adapter; |
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#define EDID_LENGTH 128 |
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#define DDC_ADDR 0x50 |
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#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ |
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#define CEA_EXT 0x02 |
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#define VTB_EXT 0x10 |
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#define DI_EXT 0x40 |
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#define LS_EXT 0x50 |
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#define MI_EXT 0x60 |
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#define DISPLAYID_EXT 0x70 |
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struct est_timings { |
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u8 t1; |
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u8 t2; |
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u8 mfg_rsvd; |
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} __attribute__((packed)); |
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|
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/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ |
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#define EDID_TIMING_ASPECT_SHIFT 6 |
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#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) |
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|
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/* need to add 60 */ |
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#define EDID_TIMING_VFREQ_SHIFT 0 |
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#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) |
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struct std_timing { |
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u8 hsize; /* need to multiply by 8 then add 248 */ |
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u8 vfreq_aspect; |
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} __attribute__((packed)); |
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#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) |
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#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) |
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#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) |
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#define DRM_EDID_PT_STEREO (1 << 5) |
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#define DRM_EDID_PT_INTERLACED (1 << 7) |
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|
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/* If detailed data is pixel timing */ |
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struct detailed_pixel_timing { |
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u8 hactive_lo; |
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u8 hblank_lo; |
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u8 hactive_hblank_hi; |
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u8 vactive_lo; |
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u8 vblank_lo; |
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u8 vactive_vblank_hi; |
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u8 hsync_offset_lo; |
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u8 hsync_pulse_width_lo; |
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u8 vsync_offset_pulse_width_lo; |
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u8 hsync_vsync_offset_pulse_width_hi; |
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u8 width_mm_lo; |
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u8 height_mm_lo; |
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u8 width_height_mm_hi; |
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u8 hborder; |
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u8 vborder; |
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u8 misc; |
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} __attribute__((packed)); |
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|
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/* If it's not pixel timing, it'll be one of the below */ |
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struct detailed_data_string { |
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u8 str[13]; |
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} __attribute__((packed)); |
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#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 |
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#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 |
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#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 |
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#define DRM_EDID_CVT_SUPPORT_FLAG 0x04 |
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struct detailed_data_monitor_range { |
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u8 min_vfreq; |
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u8 max_vfreq; |
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u8 min_hfreq_khz; |
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u8 max_hfreq_khz; |
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u8 pixel_clock_mhz; /* need to multiply by 10 */ |
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u8 flags; |
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union { |
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struct { |
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u8 reserved; |
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u8 hfreq_start_khz; /* need to multiply by 2 */ |
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u8 c; /* need to divide by 2 */ |
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__le16 m; |
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u8 k; |
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u8 j; /* need to divide by 2 */ |
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} __attribute__((packed)) gtf2; |
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struct { |
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u8 version; |
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u8 data1; /* high 6 bits: extra clock resolution */ |
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u8 data2; /* plus low 2 of above: max hactive */ |
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u8 supported_aspects; |
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u8 flags; /* preferred aspect and blanking support */ |
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u8 supported_scalings; |
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u8 preferred_refresh; |
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} __attribute__((packed)) cvt; |
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} formula; |
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} __attribute__((packed)); |
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struct detailed_data_wpindex { |
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u8 white_yx_lo; /* Lower 2 bits each */ |
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u8 white_x_hi; |
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u8 white_y_hi; |
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u8 gamma; /* need to divide by 100 then add 1 */ |
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} __attribute__((packed)); |
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struct detailed_data_color_point { |
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u8 windex1; |
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u8 wpindex1[3]; |
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u8 windex2; |
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u8 wpindex2[3]; |
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} __attribute__((packed)); |
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struct cvt_timing { |
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u8 code[3]; |
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} __attribute__((packed)); |
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struct detailed_non_pixel { |
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u8 pad1; |
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u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name |
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fb=color point data, fa=standard timing data, |
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f9=undefined, f8=mfg. reserved */ |
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u8 pad2; |
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union { |
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struct detailed_data_string str; |
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struct detailed_data_monitor_range range; |
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struct detailed_data_wpindex color; |
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struct std_timing timings[6]; |
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struct cvt_timing cvt[4]; |
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} data; |
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} __attribute__((packed)); |
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#define EDID_DETAIL_EST_TIMINGS 0xf7 |
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#define EDID_DETAIL_CVT_3BYTE 0xf8 |
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#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 |
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#define EDID_DETAIL_STD_MODES 0xfa |
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#define EDID_DETAIL_MONITOR_CPDATA 0xfb |
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#define EDID_DETAIL_MONITOR_NAME 0xfc |
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#define EDID_DETAIL_MONITOR_RANGE 0xfd |
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#define EDID_DETAIL_MONITOR_STRING 0xfe |
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#define EDID_DETAIL_MONITOR_SERIAL 0xff |
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struct detailed_timing { |
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__le16 pixel_clock; /* need to multiply by 10 KHz */ |
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union { |
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struct detailed_pixel_timing pixel_data; |
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struct detailed_non_pixel other_data; |
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} data; |
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} __attribute__((packed)); |
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#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) |
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#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) |
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#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) |
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#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) |
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#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) |
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#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) |
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#define DRM_EDID_INPUT_DIGITAL (1 << 7) |
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#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ |
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#define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ |
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#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) |
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#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) |
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#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) |
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/* If analog */ |
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#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ |
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/* If digital */ |
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#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) |
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#define DRM_EDID_FEATURE_RGB (0 << 3) |
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#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) |
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#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) |
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#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ |
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#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) |
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#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) |
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#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) |
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#define DRM_EDID_HDMI_DC_48 (1 << 6) |
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#define DRM_EDID_HDMI_DC_36 (1 << 5) |
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#define DRM_EDID_HDMI_DC_30 (1 << 4) |
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#define DRM_EDID_HDMI_DC_Y444 (1 << 3) |
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/* YCBCR 420 deep color modes */ |
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#define DRM_EDID_YCBCR420_DC_48 (1 << 2) |
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#define DRM_EDID_YCBCR420_DC_36 (1 << 1) |
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#define DRM_EDID_YCBCR420_DC_30 (1 << 0) |
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#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ |
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DRM_EDID_YCBCR420_DC_36 | \ |
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DRM_EDID_YCBCR420_DC_30) |
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/* HDMI 2.1 additional fields */ |
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#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 |
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#define DRM_EDID_FAPA_START_LOCATION (1 << 0) |
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#define DRM_EDID_ALLM (1 << 1) |
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#define DRM_EDID_FVA (1 << 2) |
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/* Deep Color specific */ |
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#define DRM_EDID_DC_30BIT_420 (1 << 0) |
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#define DRM_EDID_DC_36BIT_420 (1 << 1) |
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#define DRM_EDID_DC_48BIT_420 (1 << 2) |
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/* VRR specific */ |
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#define DRM_EDID_CNMVRR (1 << 3) |
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#define DRM_EDID_CINEMA_VRR (1 << 4) |
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#define DRM_EDID_MDELTA (1 << 5) |
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#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 |
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#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff |
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#define DRM_EDID_VRR_MIN_MASK 0x3f |
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/* DSC specific */ |
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#define DRM_EDID_DSC_10BPC (1 << 0) |
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#define DRM_EDID_DSC_12BPC (1 << 1) |
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#define DRM_EDID_DSC_16BPC (1 << 2) |
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#define DRM_EDID_DSC_ALL_BPP (1 << 3) |
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#define DRM_EDID_DSC_NATIVE_420 (1 << 6) |
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#define DRM_EDID_DSC_1P2 (1 << 7) |
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#define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 |
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#define DRM_EDID_DSC_MAX_SLICES 0xf |
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#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f |
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/* ELD Header Block */ |
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#define DRM_ELD_HEADER_BLOCK_SIZE 4 |
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#define DRM_ELD_VER 0 |
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# define DRM_ELD_VER_SHIFT 3 |
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# define DRM_ELD_VER_MASK (0x1f << 3) |
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# define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ |
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# define DRM_ELD_VER_CANNED (0x1f << 3) |
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#define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ |
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/* ELD Baseline Block for ELD_Ver == 2 */ |
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#define DRM_ELD_CEA_EDID_VER_MNL 4 |
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# define DRM_ELD_CEA_EDID_VER_SHIFT 5 |
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# define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) |
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# define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) |
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# define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) |
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# define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) |
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# define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) |
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# define DRM_ELD_MNL_SHIFT 0 |
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# define DRM_ELD_MNL_MASK (0x1f << 0) |
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#define DRM_ELD_SAD_COUNT_CONN_TYPE 5 |
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# define DRM_ELD_SAD_COUNT_SHIFT 4 |
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# define DRM_ELD_SAD_COUNT_MASK (0xf << 4) |
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# define DRM_ELD_CONN_TYPE_SHIFT 2 |
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# define DRM_ELD_CONN_TYPE_MASK (3 << 2) |
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# define DRM_ELD_CONN_TYPE_HDMI (0 << 2) |
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# define DRM_ELD_CONN_TYPE_DP (1 << 2) |
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# define DRM_ELD_SUPPORTS_AI (1 << 1) |
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# define DRM_ELD_SUPPORTS_HDCP (1 << 0) |
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#define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ |
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# define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ |
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#define DRM_ELD_SPEAKER 7 |
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# define DRM_ELD_SPEAKER_MASK 0x7f |
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# define DRM_ELD_SPEAKER_RLRC (1 << 6) |
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# define DRM_ELD_SPEAKER_FLRC (1 << 5) |
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# define DRM_ELD_SPEAKER_RC (1 << 4) |
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# define DRM_ELD_SPEAKER_RLR (1 << 3) |
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# define DRM_ELD_SPEAKER_FC (1 << 2) |
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# define DRM_ELD_SPEAKER_LFE (1 << 1) |
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# define DRM_ELD_SPEAKER_FLR (1 << 0) |
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#define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ |
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# define DRM_ELD_PORT_ID_LEN 8 |
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#define DRM_ELD_MANUFACTURER_NAME0 16 |
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#define DRM_ELD_MANUFACTURER_NAME1 17 |
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#define DRM_ELD_PRODUCT_CODE0 18 |
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#define DRM_ELD_PRODUCT_CODE1 19 |
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#define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ |
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#define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) |
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struct edid { |
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u8 header[8]; |
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/* Vendor & product info */ |
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u8 mfg_id[2]; |
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u8 prod_code[2]; |
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u32 serial; /* FIXME: byte order */ |
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u8 mfg_week; |
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u8 mfg_year; |
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/* EDID version */ |
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u8 version; |
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u8 revision; |
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/* Display info: */ |
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u8 input; |
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u8 width_cm; |
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u8 height_cm; |
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u8 gamma; |
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u8 features; |
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/* Color characteristics */ |
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u8 red_green_lo; |
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u8 black_white_lo; |
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u8 red_x; |
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u8 red_y; |
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u8 green_x; |
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u8 green_y; |
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u8 blue_x; |
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u8 blue_y; |
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u8 white_x; |
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u8 white_y; |
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/* Est. timings and mfg rsvd timings*/ |
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struct est_timings established_timings; |
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/* Standard timings 1-8*/ |
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struct std_timing standard_timings[8]; |
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/* Detailing timings 1-4 */ |
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struct detailed_timing detailed_timings[4]; |
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/* Number of 128 byte ext. blocks */ |
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u8 extensions; |
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/* Checksum */ |
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u8 checksum; |
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} __attribute__((packed)); |
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#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) |
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/* Short Audio Descriptor */ |
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struct cea_sad { |
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u8 format; |
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u8 channels; /* max number of channels - 1 */ |
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u8 freq; |
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u8 byte2; /* meaning depends on format */ |
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}; |
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struct drm_encoder; |
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struct drm_connector; |
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struct drm_connector_state; |
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struct drm_display_mode; |
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int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); |
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int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); |
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int drm_av_sync_delay(struct drm_connector *connector, |
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const struct drm_display_mode *mode); |
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#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE |
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struct edid *drm_load_edid_firmware(struct drm_connector *connector); |
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int __drm_set_edid_firmware_path(const char *path); |
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int __drm_get_edid_firmware_path(char *buf, size_t bufsize); |
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#else |
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static inline struct edid * |
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drm_load_edid_firmware(struct drm_connector *connector) |
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{ |
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return ERR_PTR(-ENOENT); |
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} |
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#endif |
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bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); |
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int |
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drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, |
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const struct drm_connector *connector, |
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const struct drm_display_mode *mode); |
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int |
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drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, |
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const struct drm_connector *connector, |
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const struct drm_display_mode *mode); |
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void |
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drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, |
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const struct drm_connector_state *conn_state); |
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void |
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drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, |
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const struct drm_connector_state *conn_state); |
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void |
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drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, |
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const struct drm_connector *connector, |
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const struct drm_display_mode *mode, |
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enum hdmi_quantization_range rgb_quant_range); |
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int |
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drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, |
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const struct drm_connector_state *conn_state); |
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/** |
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* drm_eld_mnl - Get ELD monitor name length in bytes. |
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* @eld: pointer to an eld memory structure with mnl set |
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*/ |
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static inline int drm_eld_mnl(const uint8_t *eld) |
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{ |
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return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; |
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} |
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/** |
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* drm_eld_sad - Get ELD SAD structures. |
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* @eld: pointer to an eld memory structure with sad_count set |
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*/ |
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static inline const uint8_t *drm_eld_sad(const uint8_t *eld) |
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{ |
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unsigned int ver, mnl; |
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ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; |
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if (ver != 2 && ver != 31) |
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return NULL; |
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mnl = drm_eld_mnl(eld); |
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if (mnl > 16) |
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return NULL; |
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return eld + DRM_ELD_CEA_SAD(mnl, 0); |
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} |
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/** |
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* drm_eld_sad_count - Get ELD SAD count. |
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* @eld: pointer to an eld memory structure with sad_count set |
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*/ |
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static inline int drm_eld_sad_count(const uint8_t *eld) |
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{ |
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return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> |
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DRM_ELD_SAD_COUNT_SHIFT; |
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} |
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/** |
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* drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes |
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* @eld: pointer to an eld memory structure with mnl and sad_count set |
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* |
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* This is a helper for determining the payload size of the baseline block, in |
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* bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. |
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*/ |
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static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) |
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{ |
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return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + |
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drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; |
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} |
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|
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/** |
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* drm_eld_size - Get ELD size in bytes |
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* @eld: pointer to a complete eld memory structure |
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* |
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* The returned value does not include the vendor block. It's vendor specific, |
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* and comprises of the remaining bytes in the ELD memory buffer after |
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* drm_eld_size() bytes of header and baseline block. |
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* |
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* The returned value is guaranteed to be a multiple of 4. |
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*/ |
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static inline int drm_eld_size(const uint8_t *eld) |
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{ |
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return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; |
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} |
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|
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/** |
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* drm_eld_get_spk_alloc - Get speaker allocation |
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* @eld: pointer to an ELD memory structure |
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* |
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* The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER |
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* field definitions to identify speakers. |
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*/ |
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static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld) |
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{ |
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return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK; |
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} |
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|
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/** |
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* drm_eld_get_conn_type - Get device type hdmi/dp connected |
|
* @eld: pointer to an ELD memory structure |
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* |
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* The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to |
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* identify the display type connected. |
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*/ |
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static inline u8 drm_eld_get_conn_type(const uint8_t *eld) |
|
{ |
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return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; |
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} |
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|
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bool drm_probe_ddc(struct i2c_adapter *adapter); |
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struct edid *drm_do_get_edid(struct drm_connector *connector, |
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int (*get_edid_block)(void *data, u8 *buf, unsigned int block, |
|
size_t len), |
|
void *data); |
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struct edid *drm_get_edid(struct drm_connector *connector, |
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struct i2c_adapter *adapter); |
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struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, |
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struct i2c_adapter *adapter); |
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struct edid *drm_edid_duplicate(const struct edid *edid); |
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int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); |
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int drm_add_override_edid_modes(struct drm_connector *connector); |
|
|
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u8 drm_match_cea_mode(const struct drm_display_mode *to_match); |
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bool drm_detect_hdmi_monitor(struct edid *edid); |
|
bool drm_detect_monitor_audio(struct edid *edid); |
|
enum hdmi_quantization_range |
|
drm_default_rgb_quant_range(const struct drm_display_mode *mode); |
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int drm_add_modes_noedid(struct drm_connector *connector, |
|
int hdisplay, int vdisplay); |
|
void drm_set_preferred_mode(struct drm_connector *connector, |
|
int hpref, int vpref); |
|
|
|
int drm_edid_header_is_valid(const u8 *raw_edid); |
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bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, |
|
bool *edid_corrupt); |
|
bool drm_edid_is_valid(struct edid *edid); |
|
void drm_edid_get_monitor_name(struct edid *edid, char *name, |
|
int buflen); |
|
struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
|
int hsize, int vsize, int fresh, |
|
bool rb); |
|
struct drm_display_mode * |
|
drm_display_mode_from_cea_vic(struct drm_device *dev, |
|
u8 video_code); |
|
|
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#endif /* __DRM_EDID_H__ */
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