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1146 lines
23 KiB
1146 lines
23 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* Generic I/O port emulation. |
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* |
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. |
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* Written by David Howells ([email protected]) |
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*/ |
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#ifndef __ASM_GENERIC_IO_H |
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#define __ASM_GENERIC_IO_H |
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|
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#include <asm/page.h> /* I/O is all done through memory accesses */ |
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#include <linux/string.h> /* for memset() and memcpy() */ |
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#include <linux/types.h> |
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#ifdef CONFIG_GENERIC_IOMAP |
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#include <asm-generic/iomap.h> |
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#endif |
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#include <asm/mmiowb.h> |
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#include <asm-generic/pci_iomap.h> |
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#ifndef __io_br |
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#define __io_br() barrier() |
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#endif |
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/* prevent prefetching of coherent DMA data ahead of a dma-complete */ |
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#ifndef __io_ar |
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#ifdef rmb |
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#define __io_ar(v) rmb() |
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#else |
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#define __io_ar(v) barrier() |
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#endif |
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#endif |
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/* flush writes to coherent DMA data before possibly triggering a DMA read */ |
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#ifndef __io_bw |
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#ifdef wmb |
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#define __io_bw() wmb() |
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#else |
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#define __io_bw() barrier() |
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#endif |
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#endif |
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/* serialize device access against a spin_unlock, usually handled there. */ |
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#ifndef __io_aw |
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#define __io_aw() mmiowb_set_pending() |
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#endif |
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#ifndef __io_pbw |
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#define __io_pbw() __io_bw() |
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#endif |
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#ifndef __io_paw |
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#define __io_paw() __io_aw() |
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#endif |
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#ifndef __io_pbr |
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#define __io_pbr() __io_br() |
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#endif |
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#ifndef __io_par |
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#define __io_par(v) __io_ar(v) |
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#endif |
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/* |
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* __raw_{read,write}{b,w,l,q}() access memory in native endianness. |
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* |
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* On some architectures memory mapped IO needs to be accessed differently. |
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* On the simple architectures, we just read/write the memory location |
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* directly. |
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*/ |
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#ifndef __raw_readb |
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#define __raw_readb __raw_readb |
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static inline u8 __raw_readb(const volatile void __iomem *addr) |
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{ |
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return *(const volatile u8 __force *)addr; |
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} |
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#endif |
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#ifndef __raw_readw |
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#define __raw_readw __raw_readw |
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static inline u16 __raw_readw(const volatile void __iomem *addr) |
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{ |
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return *(const volatile u16 __force *)addr; |
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} |
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#endif |
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#ifndef __raw_readl |
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#define __raw_readl __raw_readl |
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static inline u32 __raw_readl(const volatile void __iomem *addr) |
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{ |
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return *(const volatile u32 __force *)addr; |
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} |
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#endif |
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#ifdef CONFIG_64BIT |
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#ifndef __raw_readq |
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#define __raw_readq __raw_readq |
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static inline u64 __raw_readq(const volatile void __iomem *addr) |
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{ |
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return *(const volatile u64 __force *)addr; |
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} |
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#endif |
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#endif /* CONFIG_64BIT */ |
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#ifndef __raw_writeb |
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#define __raw_writeb __raw_writeb |
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static inline void __raw_writeb(u8 value, volatile void __iomem *addr) |
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{ |
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*(volatile u8 __force *)addr = value; |
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} |
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#endif |
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#ifndef __raw_writew |
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#define __raw_writew __raw_writew |
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static inline void __raw_writew(u16 value, volatile void __iomem *addr) |
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{ |
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*(volatile u16 __force *)addr = value; |
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} |
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#endif |
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#ifndef __raw_writel |
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#define __raw_writel __raw_writel |
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static inline void __raw_writel(u32 value, volatile void __iomem *addr) |
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{ |
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*(volatile u32 __force *)addr = value; |
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} |
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#endif |
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#ifdef CONFIG_64BIT |
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#ifndef __raw_writeq |
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#define __raw_writeq __raw_writeq |
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static inline void __raw_writeq(u64 value, volatile void __iomem *addr) |
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{ |
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*(volatile u64 __force *)addr = value; |
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} |
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#endif |
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#endif /* CONFIG_64BIT */ |
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/* |
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* {read,write}{b,w,l,q}() access little endian memory and return result in |
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* native endianness. |
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*/ |
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#ifndef readb |
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#define readb readb |
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static inline u8 readb(const volatile void __iomem *addr) |
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{ |
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u8 val; |
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__io_br(); |
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val = __raw_readb(addr); |
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__io_ar(val); |
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return val; |
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} |
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#endif |
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#ifndef readw |
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#define readw readw |
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static inline u16 readw(const volatile void __iomem *addr) |
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{ |
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u16 val; |
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__io_br(); |
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val = __le16_to_cpu((__le16 __force)__raw_readw(addr)); |
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__io_ar(val); |
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return val; |
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} |
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#endif |
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#ifndef readl |
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#define readl readl |
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static inline u32 readl(const volatile void __iomem *addr) |
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{ |
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u32 val; |
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__io_br(); |
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val = __le32_to_cpu((__le32 __force)__raw_readl(addr)); |
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__io_ar(val); |
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return val; |
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} |
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#endif |
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#ifdef CONFIG_64BIT |
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#ifndef readq |
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#define readq readq |
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static inline u64 readq(const volatile void __iomem *addr) |
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{ |
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u64 val; |
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__io_br(); |
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val = __le64_to_cpu(__raw_readq(addr)); |
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__io_ar(val); |
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return val; |
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} |
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#endif |
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#endif /* CONFIG_64BIT */ |
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#ifndef writeb |
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#define writeb writeb |
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static inline void writeb(u8 value, volatile void __iomem *addr) |
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{ |
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__io_bw(); |
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__raw_writeb(value, addr); |
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__io_aw(); |
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} |
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#endif |
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#ifndef writew |
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#define writew writew |
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static inline void writew(u16 value, volatile void __iomem *addr) |
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{ |
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__io_bw(); |
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__raw_writew((u16 __force)cpu_to_le16(value), addr); |
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__io_aw(); |
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} |
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#endif |
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#ifndef writel |
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#define writel writel |
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static inline void writel(u32 value, volatile void __iomem *addr) |
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{ |
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__io_bw(); |
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__raw_writel((u32 __force)__cpu_to_le32(value), addr); |
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__io_aw(); |
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} |
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#endif |
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#ifdef CONFIG_64BIT |
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#ifndef writeq |
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#define writeq writeq |
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static inline void writeq(u64 value, volatile void __iomem *addr) |
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{ |
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__io_bw(); |
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__raw_writeq(__cpu_to_le64(value), addr); |
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__io_aw(); |
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} |
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#endif |
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#endif /* CONFIG_64BIT */ |
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/* |
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* {read,write}{b,w,l,q}_relaxed() are like the regular version, but |
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* are not guaranteed to provide ordering against spinlocks or memory |
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* accesses. |
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*/ |
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#ifndef readb_relaxed |
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#define readb_relaxed readb_relaxed |
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static inline u8 readb_relaxed(const volatile void __iomem *addr) |
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{ |
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return __raw_readb(addr); |
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} |
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#endif |
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#ifndef readw_relaxed |
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#define readw_relaxed readw_relaxed |
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static inline u16 readw_relaxed(const volatile void __iomem *addr) |
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{ |
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return __le16_to_cpu(__raw_readw(addr)); |
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} |
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#endif |
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#ifndef readl_relaxed |
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#define readl_relaxed readl_relaxed |
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static inline u32 readl_relaxed(const volatile void __iomem *addr) |
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{ |
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return __le32_to_cpu(__raw_readl(addr)); |
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} |
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#endif |
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#if defined(readq) && !defined(readq_relaxed) |
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#define readq_relaxed readq_relaxed |
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static inline u64 readq_relaxed(const volatile void __iomem *addr) |
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{ |
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return __le64_to_cpu(__raw_readq(addr)); |
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} |
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#endif |
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#ifndef writeb_relaxed |
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#define writeb_relaxed writeb_relaxed |
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static inline void writeb_relaxed(u8 value, volatile void __iomem *addr) |
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{ |
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__raw_writeb(value, addr); |
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} |
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#endif |
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#ifndef writew_relaxed |
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#define writew_relaxed writew_relaxed |
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static inline void writew_relaxed(u16 value, volatile void __iomem *addr) |
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{ |
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__raw_writew(cpu_to_le16(value), addr); |
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} |
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#endif |
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#ifndef writel_relaxed |
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#define writel_relaxed writel_relaxed |
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static inline void writel_relaxed(u32 value, volatile void __iomem *addr) |
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{ |
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__raw_writel(__cpu_to_le32(value), addr); |
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} |
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#endif |
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#if defined(writeq) && !defined(writeq_relaxed) |
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#define writeq_relaxed writeq_relaxed |
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static inline void writeq_relaxed(u64 value, volatile void __iomem *addr) |
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{ |
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__raw_writeq(__cpu_to_le64(value), addr); |
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} |
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#endif |
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/* |
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* {read,write}s{b,w,l,q}() repeatedly access the same memory address in |
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* native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). |
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*/ |
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#ifndef readsb |
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#define readsb readsb |
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static inline void readsb(const volatile void __iomem *addr, void *buffer, |
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unsigned int count) |
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{ |
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if (count) { |
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u8 *buf = buffer; |
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do { |
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u8 x = __raw_readb(addr); |
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*buf++ = x; |
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} while (--count); |
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} |
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} |
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#endif |
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#ifndef readsw |
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#define readsw readsw |
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static inline void readsw(const volatile void __iomem *addr, void *buffer, |
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unsigned int count) |
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{ |
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if (count) { |
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u16 *buf = buffer; |
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do { |
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u16 x = __raw_readw(addr); |
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*buf++ = x; |
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} while (--count); |
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} |
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} |
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#endif |
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#ifndef readsl |
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#define readsl readsl |
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static inline void readsl(const volatile void __iomem *addr, void *buffer, |
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unsigned int count) |
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{ |
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if (count) { |
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u32 *buf = buffer; |
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do { |
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u32 x = __raw_readl(addr); |
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*buf++ = x; |
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} while (--count); |
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} |
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} |
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#endif |
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#ifdef CONFIG_64BIT |
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#ifndef readsq |
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#define readsq readsq |
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static inline void readsq(const volatile void __iomem *addr, void *buffer, |
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unsigned int count) |
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{ |
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if (count) { |
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u64 *buf = buffer; |
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do { |
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u64 x = __raw_readq(addr); |
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*buf++ = x; |
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} while (--count); |
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} |
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} |
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#endif |
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#endif /* CONFIG_64BIT */ |
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#ifndef writesb |
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#define writesb writesb |
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static inline void writesb(volatile void __iomem *addr, const void *buffer, |
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unsigned int count) |
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{ |
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if (count) { |
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const u8 *buf = buffer; |
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do { |
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__raw_writeb(*buf++, addr); |
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} while (--count); |
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} |
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} |
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#endif |
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#ifndef writesw |
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#define writesw writesw |
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static inline void writesw(volatile void __iomem *addr, const void *buffer, |
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unsigned int count) |
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{ |
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if (count) { |
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const u16 *buf = buffer; |
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do { |
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__raw_writew(*buf++, addr); |
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} while (--count); |
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} |
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} |
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#endif |
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#ifndef writesl |
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#define writesl writesl |
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static inline void writesl(volatile void __iomem *addr, const void *buffer, |
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unsigned int count) |
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{ |
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if (count) { |
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const u32 *buf = buffer; |
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do { |
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__raw_writel(*buf++, addr); |
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} while (--count); |
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} |
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} |
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#endif |
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#ifdef CONFIG_64BIT |
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#ifndef writesq |
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#define writesq writesq |
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static inline void writesq(volatile void __iomem *addr, const void *buffer, |
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unsigned int count) |
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{ |
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if (count) { |
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const u64 *buf = buffer; |
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do { |
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__raw_writeq(*buf++, addr); |
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} while (--count); |
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} |
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} |
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#endif |
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#endif /* CONFIG_64BIT */ |
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#ifndef PCI_IOBASE |
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#define PCI_IOBASE ((void __iomem *)0) |
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#endif |
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#ifndef IO_SPACE_LIMIT |
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#define IO_SPACE_LIMIT 0xffff |
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#endif |
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/* |
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* {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be |
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* implemented on hardware that needs an additional delay for I/O accesses to |
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* take effect. |
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*/ |
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#if !defined(inb) && !defined(_inb) |
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#define _inb _inb |
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static inline u8 _inb(unsigned long addr) |
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{ |
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u8 val; |
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__io_pbr(); |
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val = __raw_readb(PCI_IOBASE + addr); |
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__io_par(val); |
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return val; |
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} |
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#endif |
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#if !defined(inw) && !defined(_inw) |
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#define _inw _inw |
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static inline u16 _inw(unsigned long addr) |
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{ |
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u16 val; |
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__io_pbr(); |
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val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr)); |
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__io_par(val); |
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return val; |
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} |
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#endif |
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#if !defined(inl) && !defined(_inl) |
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#define _inl _inl |
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static inline u32 _inl(unsigned long addr) |
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{ |
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u32 val; |
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__io_pbr(); |
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val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr)); |
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__io_par(val); |
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return val; |
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} |
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#endif |
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#if !defined(outb) && !defined(_outb) |
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#define _outb _outb |
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static inline void _outb(u8 value, unsigned long addr) |
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{ |
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__io_pbw(); |
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__raw_writeb(value, PCI_IOBASE + addr); |
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__io_paw(); |
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} |
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#endif |
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#if !defined(outw) && !defined(_outw) |
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#define _outw _outw |
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static inline void _outw(u16 value, unsigned long addr) |
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{ |
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__io_pbw(); |
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__raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr); |
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__io_paw(); |
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} |
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#endif |
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#if !defined(outl) && !defined(_outl) |
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#define _outl _outl |
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static inline void _outl(u32 value, unsigned long addr) |
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{ |
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__io_pbw(); |
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__raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr); |
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__io_paw(); |
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} |
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#endif |
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#include <linux/logic_pio.h> |
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#ifndef inb |
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#define inb _inb |
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#endif |
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#ifndef inw |
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#define inw _inw |
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#endif |
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#ifndef inl |
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#define inl _inl |
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#endif |
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|
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#ifndef outb |
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#define outb _outb |
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#endif |
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#ifndef outw |
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#define outw _outw |
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#endif |
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#ifndef outl |
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#define outl _outl |
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#endif |
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|
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#ifndef inb_p |
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#define inb_p inb_p |
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static inline u8 inb_p(unsigned long addr) |
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{ |
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return inb(addr); |
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} |
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#endif |
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|
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#ifndef inw_p |
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#define inw_p inw_p |
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static inline u16 inw_p(unsigned long addr) |
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{ |
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return inw(addr); |
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} |
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#endif |
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|
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#ifndef inl_p |
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#define inl_p inl_p |
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static inline u32 inl_p(unsigned long addr) |
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{ |
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return inl(addr); |
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} |
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#endif |
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|
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#ifndef outb_p |
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#define outb_p outb_p |
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static inline void outb_p(u8 value, unsigned long addr) |
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{ |
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outb(value, addr); |
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} |
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#endif |
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|
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#ifndef outw_p |
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#define outw_p outw_p |
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static inline void outw_p(u16 value, unsigned long addr) |
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{ |
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outw(value, addr); |
|
} |
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#endif |
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|
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#ifndef outl_p |
|
#define outl_p outl_p |
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static inline void outl_p(u32 value, unsigned long addr) |
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{ |
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outl(value, addr); |
|
} |
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#endif |
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|
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/* |
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* {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a |
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* single I/O port multiple times. |
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*/ |
|
|
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#ifndef insb |
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#define insb insb |
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static inline void insb(unsigned long addr, void *buffer, unsigned int count) |
|
{ |
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readsb(PCI_IOBASE + addr, buffer, count); |
|
} |
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#endif |
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|
|
#ifndef insw |
|
#define insw insw |
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static inline void insw(unsigned long addr, void *buffer, unsigned int count) |
|
{ |
|
readsw(PCI_IOBASE + addr, buffer, count); |
|
} |
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#endif |
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|
|
#ifndef insl |
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#define insl insl |
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static inline void insl(unsigned long addr, void *buffer, unsigned int count) |
|
{ |
|
readsl(PCI_IOBASE + addr, buffer, count); |
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} |
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#endif |
|
|
|
#ifndef outsb |
|
#define outsb outsb |
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static inline void outsb(unsigned long addr, const void *buffer, |
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unsigned int count) |
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{ |
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writesb(PCI_IOBASE + addr, buffer, count); |
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} |
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#endif |
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|
|
#ifndef outsw |
|
#define outsw outsw |
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static inline void outsw(unsigned long addr, const void *buffer, |
|
unsigned int count) |
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{ |
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writesw(PCI_IOBASE + addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef outsl |
|
#define outsl outsl |
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static inline void outsl(unsigned long addr, const void *buffer, |
|
unsigned int count) |
|
{ |
|
writesl(PCI_IOBASE + addr, buffer, count); |
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} |
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#endif |
|
|
|
#ifndef insb_p |
|
#define insb_p insb_p |
|
static inline void insb_p(unsigned long addr, void *buffer, unsigned int count) |
|
{ |
|
insb(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef insw_p |
|
#define insw_p insw_p |
|
static inline void insw_p(unsigned long addr, void *buffer, unsigned int count) |
|
{ |
|
insw(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef insl_p |
|
#define insl_p insl_p |
|
static inline void insl_p(unsigned long addr, void *buffer, unsigned int count) |
|
{ |
|
insl(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef outsb_p |
|
#define outsb_p outsb_p |
|
static inline void outsb_p(unsigned long addr, const void *buffer, |
|
unsigned int count) |
|
{ |
|
outsb(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef outsw_p |
|
#define outsw_p outsw_p |
|
static inline void outsw_p(unsigned long addr, const void *buffer, |
|
unsigned int count) |
|
{ |
|
outsw(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef outsl_p |
|
#define outsl_p outsl_p |
|
static inline void outsl_p(unsigned long addr, const void *buffer, |
|
unsigned int count) |
|
{ |
|
outsl(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef CONFIG_GENERIC_IOMAP |
|
#ifndef ioread8 |
|
#define ioread8 ioread8 |
|
static inline u8 ioread8(const volatile void __iomem *addr) |
|
{ |
|
return readb(addr); |
|
} |
|
#endif |
|
|
|
#ifndef ioread16 |
|
#define ioread16 ioread16 |
|
static inline u16 ioread16(const volatile void __iomem *addr) |
|
{ |
|
return readw(addr); |
|
} |
|
#endif |
|
|
|
#ifndef ioread32 |
|
#define ioread32 ioread32 |
|
static inline u32 ioread32(const volatile void __iomem *addr) |
|
{ |
|
return readl(addr); |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_64BIT |
|
#ifndef ioread64 |
|
#define ioread64 ioread64 |
|
static inline u64 ioread64(const volatile void __iomem *addr) |
|
{ |
|
return readq(addr); |
|
} |
|
#endif |
|
#endif /* CONFIG_64BIT */ |
|
|
|
#ifndef iowrite8 |
|
#define iowrite8 iowrite8 |
|
static inline void iowrite8(u8 value, volatile void __iomem *addr) |
|
{ |
|
writeb(value, addr); |
|
} |
|
#endif |
|
|
|
#ifndef iowrite16 |
|
#define iowrite16 iowrite16 |
|
static inline void iowrite16(u16 value, volatile void __iomem *addr) |
|
{ |
|
writew(value, addr); |
|
} |
|
#endif |
|
|
|
#ifndef iowrite32 |
|
#define iowrite32 iowrite32 |
|
static inline void iowrite32(u32 value, volatile void __iomem *addr) |
|
{ |
|
writel(value, addr); |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_64BIT |
|
#ifndef iowrite64 |
|
#define iowrite64 iowrite64 |
|
static inline void iowrite64(u64 value, volatile void __iomem *addr) |
|
{ |
|
writeq(value, addr); |
|
} |
|
#endif |
|
#endif /* CONFIG_64BIT */ |
|
|
|
#ifndef ioread16be |
|
#define ioread16be ioread16be |
|
static inline u16 ioread16be(const volatile void __iomem *addr) |
|
{ |
|
return swab16(readw(addr)); |
|
} |
|
#endif |
|
|
|
#ifndef ioread32be |
|
#define ioread32be ioread32be |
|
static inline u32 ioread32be(const volatile void __iomem *addr) |
|
{ |
|
return swab32(readl(addr)); |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_64BIT |
|
#ifndef ioread64be |
|
#define ioread64be ioread64be |
|
static inline u64 ioread64be(const volatile void __iomem *addr) |
|
{ |
|
return swab64(readq(addr)); |
|
} |
|
#endif |
|
#endif /* CONFIG_64BIT */ |
|
|
|
#ifndef iowrite16be |
|
#define iowrite16be iowrite16be |
|
static inline void iowrite16be(u16 value, void volatile __iomem *addr) |
|
{ |
|
writew(swab16(value), addr); |
|
} |
|
#endif |
|
|
|
#ifndef iowrite32be |
|
#define iowrite32be iowrite32be |
|
static inline void iowrite32be(u32 value, volatile void __iomem *addr) |
|
{ |
|
writel(swab32(value), addr); |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_64BIT |
|
#ifndef iowrite64be |
|
#define iowrite64be iowrite64be |
|
static inline void iowrite64be(u64 value, volatile void __iomem *addr) |
|
{ |
|
writeq(swab64(value), addr); |
|
} |
|
#endif |
|
#endif /* CONFIG_64BIT */ |
|
|
|
#ifndef ioread8_rep |
|
#define ioread8_rep ioread8_rep |
|
static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer, |
|
unsigned int count) |
|
{ |
|
readsb(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef ioread16_rep |
|
#define ioread16_rep ioread16_rep |
|
static inline void ioread16_rep(const volatile void __iomem *addr, |
|
void *buffer, unsigned int count) |
|
{ |
|
readsw(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef ioread32_rep |
|
#define ioread32_rep ioread32_rep |
|
static inline void ioread32_rep(const volatile void __iomem *addr, |
|
void *buffer, unsigned int count) |
|
{ |
|
readsl(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_64BIT |
|
#ifndef ioread64_rep |
|
#define ioread64_rep ioread64_rep |
|
static inline void ioread64_rep(const volatile void __iomem *addr, |
|
void *buffer, unsigned int count) |
|
{ |
|
readsq(addr, buffer, count); |
|
} |
|
#endif |
|
#endif /* CONFIG_64BIT */ |
|
|
|
#ifndef iowrite8_rep |
|
#define iowrite8_rep iowrite8_rep |
|
static inline void iowrite8_rep(volatile void __iomem *addr, |
|
const void *buffer, |
|
unsigned int count) |
|
{ |
|
writesb(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef iowrite16_rep |
|
#define iowrite16_rep iowrite16_rep |
|
static inline void iowrite16_rep(volatile void __iomem *addr, |
|
const void *buffer, |
|
unsigned int count) |
|
{ |
|
writesw(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifndef iowrite32_rep |
|
#define iowrite32_rep iowrite32_rep |
|
static inline void iowrite32_rep(volatile void __iomem *addr, |
|
const void *buffer, |
|
unsigned int count) |
|
{ |
|
writesl(addr, buffer, count); |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_64BIT |
|
#ifndef iowrite64_rep |
|
#define iowrite64_rep iowrite64_rep |
|
static inline void iowrite64_rep(volatile void __iomem *addr, |
|
const void *buffer, |
|
unsigned int count) |
|
{ |
|
writesq(addr, buffer, count); |
|
} |
|
#endif |
|
#endif /* CONFIG_64BIT */ |
|
#endif /* CONFIG_GENERIC_IOMAP */ |
|
|
|
#ifdef __KERNEL__ |
|
|
|
#include <linux/vmalloc.h> |
|
#define __io_virt(x) ((void __force *)(x)) |
|
|
|
/* |
|
* Change virtual addresses to physical addresses and vv. |
|
* These are pretty trivial |
|
*/ |
|
#ifndef virt_to_phys |
|
#define virt_to_phys virt_to_phys |
|
static inline unsigned long virt_to_phys(volatile void *address) |
|
{ |
|
return __pa((unsigned long)address); |
|
} |
|
#endif |
|
|
|
#ifndef phys_to_virt |
|
#define phys_to_virt phys_to_virt |
|
static inline void *phys_to_virt(unsigned long address) |
|
{ |
|
return __va(address); |
|
} |
|
#endif |
|
|
|
/** |
|
* DOC: ioremap() and ioremap_*() variants |
|
* |
|
* Architectures with an MMU are expected to provide ioremap() and iounmap() |
|
* themselves or rely on GENERIC_IOREMAP. For NOMMU architectures we provide |
|
* a default nop-op implementation that expect that the physical address used |
|
* for MMIO are already marked as uncached, and can be used as kernel virtual |
|
* addresses. |
|
* |
|
* ioremap_wc() and ioremap_wt() can provide more relaxed caching attributes |
|
* for specific drivers if the architecture choses to implement them. If they |
|
* are not implemented we fall back to plain ioremap. |
|
*/ |
|
#ifndef CONFIG_MMU |
|
#ifndef ioremap |
|
#define ioremap ioremap |
|
static inline void __iomem *ioremap(phys_addr_t offset, size_t size) |
|
{ |
|
return (void __iomem *)(unsigned long)offset; |
|
} |
|
#endif |
|
|
|
#ifndef iounmap |
|
#define iounmap iounmap |
|
static inline void iounmap(void __iomem *addr) |
|
{ |
|
} |
|
#endif |
|
#elif defined(CONFIG_GENERIC_IOREMAP) |
|
#include <linux/pgtable.h> |
|
|
|
void __iomem *ioremap_prot(phys_addr_t addr, size_t size, unsigned long prot); |
|
void iounmap(volatile void __iomem *addr); |
|
|
|
static inline void __iomem *ioremap(phys_addr_t addr, size_t size) |
|
{ |
|
/* _PAGE_IOREMAP needs to be supplied by the architecture */ |
|
return ioremap_prot(addr, size, _PAGE_IOREMAP); |
|
} |
|
#endif /* !CONFIG_MMU || CONFIG_GENERIC_IOREMAP */ |
|
|
|
#ifndef ioremap_wc |
|
#define ioremap_wc ioremap |
|
#endif |
|
|
|
#ifndef ioremap_wt |
|
#define ioremap_wt ioremap |
|
#endif |
|
|
|
/* |
|
* ioremap_uc is special in that we do require an explicit architecture |
|
* implementation. In general you do not want to use this function in a |
|
* driver and use plain ioremap, which is uncached by default. Similarly |
|
* architectures should not implement it unless they have a very good |
|
* reason. |
|
*/ |
|
#ifndef ioremap_uc |
|
#define ioremap_uc ioremap_uc |
|
static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size) |
|
{ |
|
return NULL; |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_HAS_IOPORT_MAP |
|
#ifndef CONFIG_GENERIC_IOMAP |
|
#ifndef ioport_map |
|
#define ioport_map ioport_map |
|
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) |
|
{ |
|
port &= IO_SPACE_LIMIT; |
|
return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port; |
|
} |
|
#define __pci_ioport_unmap __pci_ioport_unmap |
|
static inline void __pci_ioport_unmap(void __iomem *p) |
|
{ |
|
uintptr_t start = (uintptr_t) PCI_IOBASE; |
|
uintptr_t addr = (uintptr_t) p; |
|
|
|
if (addr >= start && addr < start + IO_SPACE_LIMIT) |
|
return; |
|
iounmap(p); |
|
} |
|
#endif |
|
|
|
#ifndef ioport_unmap |
|
#define ioport_unmap ioport_unmap |
|
static inline void ioport_unmap(void __iomem *p) |
|
{ |
|
} |
|
#endif |
|
#else /* CONFIG_GENERIC_IOMAP */ |
|
extern void __iomem *ioport_map(unsigned long port, unsigned int nr); |
|
extern void ioport_unmap(void __iomem *p); |
|
#endif /* CONFIG_GENERIC_IOMAP */ |
|
#endif /* CONFIG_HAS_IOPORT_MAP */ |
|
|
|
#ifndef CONFIG_GENERIC_IOMAP |
|
struct pci_dev; |
|
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); |
|
|
|
#ifndef __pci_ioport_unmap |
|
static inline void __pci_ioport_unmap(void __iomem *p) {} |
|
#endif |
|
|
|
#ifndef pci_iounmap |
|
#define pci_iounmap pci_iounmap |
|
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) |
|
{ |
|
__pci_ioport_unmap(p); |
|
} |
|
#endif |
|
#endif /* CONFIG_GENERIC_IOMAP */ |
|
|
|
/* |
|
* Convert a virtual cached pointer to an uncached pointer |
|
*/ |
|
#ifndef xlate_dev_kmem_ptr |
|
#define xlate_dev_kmem_ptr xlate_dev_kmem_ptr |
|
static inline void *xlate_dev_kmem_ptr(void *addr) |
|
{ |
|
return addr; |
|
} |
|
#endif |
|
|
|
#ifndef xlate_dev_mem_ptr |
|
#define xlate_dev_mem_ptr xlate_dev_mem_ptr |
|
static inline void *xlate_dev_mem_ptr(phys_addr_t addr) |
|
{ |
|
return __va(addr); |
|
} |
|
#endif |
|
|
|
#ifndef unxlate_dev_mem_ptr |
|
#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr |
|
static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr) |
|
{ |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_VIRT_TO_BUS |
|
#ifndef virt_to_bus |
|
static inline unsigned long virt_to_bus(void *address) |
|
{ |
|
return (unsigned long)address; |
|
} |
|
|
|
static inline void *bus_to_virt(unsigned long address) |
|
{ |
|
return (void *)address; |
|
} |
|
#endif |
|
#endif |
|
|
|
#ifndef memset_io |
|
#define memset_io memset_io |
|
/** |
|
* memset_io Set a range of I/O memory to a constant value |
|
* @addr: The beginning of the I/O-memory range to set |
|
* @val: The value to set the memory to |
|
* @count: The number of bytes to set |
|
* |
|
* Set a range of I/O memory to a given value. |
|
*/ |
|
static inline void memset_io(volatile void __iomem *addr, int value, |
|
size_t size) |
|
{ |
|
memset(__io_virt(addr), value, size); |
|
} |
|
#endif |
|
|
|
#ifndef memcpy_fromio |
|
#define memcpy_fromio memcpy_fromio |
|
/** |
|
* memcpy_fromio Copy a block of data from I/O memory |
|
* @dst: The (RAM) destination for the copy |
|
* @src: The (I/O memory) source for the data |
|
* @count: The number of bytes to copy |
|
* |
|
* Copy a block of data from I/O memory. |
|
*/ |
|
static inline void memcpy_fromio(void *buffer, |
|
const volatile void __iomem *addr, |
|
size_t size) |
|
{ |
|
memcpy(buffer, __io_virt(addr), size); |
|
} |
|
#endif |
|
|
|
#ifndef memcpy_toio |
|
#define memcpy_toio memcpy_toio |
|
/** |
|
* memcpy_toio Copy a block of data into I/O memory |
|
* @dst: The (I/O memory) destination for the copy |
|
* @src: The (RAM) source for the data |
|
* @count: The number of bytes to copy |
|
* |
|
* Copy a block of data to I/O memory. |
|
*/ |
|
static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer, |
|
size_t size) |
|
{ |
|
memcpy(__io_virt(addr), buffer, size); |
|
} |
|
#endif |
|
|
|
#ifndef CONFIG_GENERIC_DEVMEM_IS_ALLOWED |
|
extern int devmem_is_allowed(unsigned long pfn); |
|
#endif |
|
|
|
#endif /* __KERNEL__ */ |
|
|
|
#endif /* __ASM_GENERIC_IO_H */
|
|
|