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677 lines
22 KiB
677 lines
22 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
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* Copyright (C) 2019-2021 Linaro Ltd. |
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*/ |
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#include <linux/types.h> |
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#include <linux/device.h> |
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#include <linux/slab.h> |
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#include <linux/bitfield.h> |
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#include <linux/dma-direction.h> |
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#include "gsi.h" |
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#include "gsi_trans.h" |
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#include "ipa.h" |
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#include "ipa_endpoint.h" |
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#include "ipa_table.h" |
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#include "ipa_cmd.h" |
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#include "ipa_mem.h" |
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/** |
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* DOC: IPA Immediate Commands |
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* |
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* The AP command TX endpoint is used to issue immediate commands to the IPA. |
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* An immediate command is generally used to request the IPA do something |
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* other than data transfer to another endpoint. |
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* |
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* Immediate commands are represented by GSI transactions just like other |
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* transfer requests, represented by a single GSI TRE. Each immediate |
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* command has a well-defined format, having a payload of a known length. |
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* This allows the transfer element's length field to be used to hold an |
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* immediate command's opcode. The payload for a command resides in DRAM |
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* and is described by a single scatterlist entry in its transaction. |
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* Commands do not require a transaction completion callback. To commit |
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* an immediate command transaction, either gsi_trans_commit_wait() or |
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* gsi_trans_commit_wait_timeout() is used. |
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*/ |
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/* Some commands can wait until indicated pipeline stages are clear */ |
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enum pipeline_clear_options { |
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pipeline_clear_hps = 0x0, |
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pipeline_clear_src_grp = 0x1, |
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pipeline_clear_full = 0x2, |
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}; |
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/* IPA_CMD_IP_V{4,6}_{FILTER,ROUTING}_INIT */ |
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struct ipa_cmd_hw_ip_fltrt_init { |
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__le64 hash_rules_addr; |
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__le64 flags; |
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__le64 nhash_rules_addr; |
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}; |
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/* Field masks for ipa_cmd_hw_ip_fltrt_init structure fields */ |
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#define IP_FLTRT_FLAGS_HASH_SIZE_FMASK GENMASK_ULL(11, 0) |
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#define IP_FLTRT_FLAGS_HASH_ADDR_FMASK GENMASK_ULL(27, 12) |
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#define IP_FLTRT_FLAGS_NHASH_SIZE_FMASK GENMASK_ULL(39, 28) |
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#define IP_FLTRT_FLAGS_NHASH_ADDR_FMASK GENMASK_ULL(55, 40) |
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/* IPA_CMD_HDR_INIT_LOCAL */ |
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struct ipa_cmd_hw_hdr_init_local { |
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__le64 hdr_table_addr; |
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__le32 flags; |
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__le32 reserved; |
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}; |
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/* Field masks for ipa_cmd_hw_hdr_init_local structure fields */ |
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#define HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK GENMASK(11, 0) |
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#define HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK GENMASK(27, 12) |
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/* IPA_CMD_REGISTER_WRITE */ |
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/* For IPA v4.0+, this opcode gets modified with pipeline clear options */ |
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#define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8) |
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#define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9) |
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struct ipa_cmd_register_write { |
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__le16 flags; /* Unused/reserved for IPA v3.5.1 */ |
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__le16 offset; |
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__le32 value; |
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__le32 value_mask; |
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__le32 clear_options; /* Unused/reserved for IPA v4.0+ */ |
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}; |
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/* Field masks for ipa_cmd_register_write structure fields */ |
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/* The next field is present for IPA v4.0 and above */ |
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#define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11) |
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/* The next field is present for IPA v3.5.1 only */ |
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#define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15) |
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/* The next field and its values are present for IPA v3.5.1 only */ |
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#define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0) |
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/* IPA_CMD_IP_PACKET_INIT */ |
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struct ipa_cmd_ip_packet_init { |
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u8 dest_endpoint; |
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u8 reserved[7]; |
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}; |
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/* Field masks for ipa_cmd_ip_packet_init dest_endpoint field */ |
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#define IPA_PACKET_INIT_DEST_ENDPOINT_FMASK GENMASK(4, 0) |
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/* IPA_CMD_DMA_SHARED_MEM */ |
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/* For IPA v4.0+, this opcode gets modified with pipeline clear options */ |
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#define DMA_SHARED_MEM_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8) |
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#define DMA_SHARED_MEM_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9) |
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struct ipa_cmd_hw_dma_mem_mem { |
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__le16 clear_after_read; /* 0 or DMA_SHARED_MEM_CLEAR_AFTER_READ */ |
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__le16 size; |
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__le16 local_addr; |
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__le16 flags; |
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__le64 system_addr; |
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}; |
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/* Flag allowing atomic clear of target region after reading data (v4.0+)*/ |
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#define DMA_SHARED_MEM_CLEAR_AFTER_READ GENMASK(15, 15) |
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/* Field masks for ipa_cmd_hw_dma_mem_mem structure fields */ |
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#define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0) |
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/* The next two fields are present for IPA v3.5.1 only. */ |
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#define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1) |
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#define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2) |
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/* IPA_CMD_IP_PACKET_TAG_STATUS */ |
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struct ipa_cmd_ip_packet_tag_status { |
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__le64 tag; |
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}; |
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#define IP_PACKET_TAG_STATUS_TAG_FMASK GENMASK_ULL(63, 16) |
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/* Immediate command payload */ |
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union ipa_cmd_payload { |
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struct ipa_cmd_hw_ip_fltrt_init table_init; |
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struct ipa_cmd_hw_hdr_init_local hdr_init_local; |
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struct ipa_cmd_register_write register_write; |
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struct ipa_cmd_ip_packet_init ip_packet_init; |
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struct ipa_cmd_hw_dma_mem_mem dma_shared_mem; |
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struct ipa_cmd_ip_packet_tag_status ip_packet_tag_status; |
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}; |
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static void ipa_cmd_validate_build(void) |
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{ |
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/* The sizes of a filter and route tables need to fit into fields |
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* in the ipa_cmd_hw_ip_fltrt_init structure. Although hashed tables |
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* might not be used, non-hashed and hashed tables have the same |
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* maximum size. IPv4 and IPv6 filter tables have the same number |
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* of entries, as and IPv4 and IPv6 route tables have the same number |
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* of entries. |
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*/ |
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#define TABLE_SIZE (TABLE_COUNT_MAX * IPA_TABLE_ENTRY_SIZE) |
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#define TABLE_COUNT_MAX max_t(u32, IPA_ROUTE_COUNT_MAX, IPA_FILTER_COUNT_MAX) |
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BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK)); |
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BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK)); |
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#undef TABLE_COUNT_MAX |
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#undef TABLE_SIZE |
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} |
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#ifdef IPA_VALIDATE |
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/* Validate a memory region holding a table */ |
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bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem, |
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bool route, bool ipv6, bool hashed) |
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{ |
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struct device *dev = &ipa->pdev->dev; |
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u32 offset_max; |
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offset_max = hashed ? field_max(IP_FLTRT_FLAGS_HASH_ADDR_FMASK) |
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: field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK); |
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if (mem->offset > offset_max || |
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ipa->mem_offset > offset_max - mem->offset) { |
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dev_err(dev, "IPv%c %s%s table region offset too large\n", |
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ipv6 ? '6' : '4', hashed ? "hashed " : "", |
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route ? "route" : "filter"); |
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dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", |
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ipa->mem_offset, mem->offset, offset_max); |
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return false; |
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} |
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if (mem->offset > ipa->mem_size || |
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mem->size > ipa->mem_size - mem->offset) { |
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dev_err(dev, "IPv%c %s%s table region out of range\n", |
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ipv6 ? '6' : '4', hashed ? "hashed " : "", |
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route ? "route" : "filter"); |
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dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", |
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mem->offset, mem->size, ipa->mem_size); |
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return false; |
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} |
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return true; |
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} |
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/* Validate the memory region that holds headers */ |
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static bool ipa_cmd_header_valid(struct ipa *ipa) |
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{ |
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const struct ipa_mem *mem = &ipa->mem[IPA_MEM_MODEM_HEADER]; |
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struct device *dev = &ipa->pdev->dev; |
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u32 offset_max; |
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u32 size_max; |
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u32 size; |
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/* In ipa_cmd_hdr_init_local_add() we record the offset and size |
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* of the header table memory area. Make sure the offset and size |
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* fit in the fields that need to hold them, and that the entire |
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* range is within the overall IPA memory range. |
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*/ |
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offset_max = field_max(HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK); |
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if (mem->offset > offset_max || |
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ipa->mem_offset > offset_max - mem->offset) { |
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dev_err(dev, "header table region offset too large\n"); |
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dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", |
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ipa->mem_offset, mem->offset, offset_max); |
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return false; |
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} |
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size_max = field_max(HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK); |
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size = ipa->mem[IPA_MEM_MODEM_HEADER].size; |
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size += ipa->mem[IPA_MEM_AP_HEADER].size; |
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if (size > size_max) { |
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dev_err(dev, "header table region size too large\n"); |
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dev_err(dev, " (0x%04x > 0x%08x)\n", size, size_max); |
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return false; |
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} |
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if (size > ipa->mem_size || mem->offset > ipa->mem_size - size) { |
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dev_err(dev, "header table region out of range\n"); |
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dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", |
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mem->offset, size, ipa->mem_size); |
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return false; |
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} |
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return true; |
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} |
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/* Indicate whether an offset can be used with a register_write command */ |
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static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa, |
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const char *name, u32 offset) |
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{ |
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struct ipa_cmd_register_write *payload; |
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struct device *dev = &ipa->pdev->dev; |
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u32 offset_max; |
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u32 bit_count; |
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/* The maximum offset in a register_write immediate command depends |
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* on the version of IPA. IPA v3.5.1 supports a 16 bit offset, but |
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* newer versions allow some additional high-order bits. |
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*/ |
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bit_count = BITS_PER_BYTE * sizeof(payload->offset); |
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if (ipa->version != IPA_VERSION_3_5_1) |
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bit_count += hweight32(REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK); |
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BUILD_BUG_ON(bit_count > 32); |
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offset_max = ~0U >> (32 - bit_count); |
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/* Make sure the offset can be represented by the field(s) |
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* that holds it. Also make sure the offset is not outside |
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* the overall IPA memory range. |
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*/ |
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if (offset > offset_max || ipa->mem_offset > offset_max - offset) { |
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dev_err(dev, "%s offset too large 0x%04x + 0x%04x > 0x%04x)\n", |
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name, ipa->mem_offset, offset, offset_max); |
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return false; |
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} |
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return true; |
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} |
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/* Check whether offsets passed to register_write are valid */ |
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static bool ipa_cmd_register_write_valid(struct ipa *ipa) |
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{ |
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const char *name; |
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u32 offset; |
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/* If hashed tables are supported, ensure the hash flush register |
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* offset will fit in a register write IPA immediate command. |
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*/ |
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if (ipa_table_hash_support(ipa)) { |
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offset = ipa_reg_filt_rout_hash_flush_offset(ipa->version); |
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name = "filter/route hash flush"; |
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if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) |
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return false; |
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} |
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/* Each endpoint can have a status endpoint associated with it, |
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* and this is recorded in an endpoint register. If the modem |
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* crashes, we reset the status endpoint for all modem endpoints |
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* using a register write IPA immediate command. Make sure the |
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* worst case (highest endpoint number) offset of that endpoint |
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* fits in the register write command field(s) that must hold it. |
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*/ |
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offset = IPA_REG_ENDP_STATUS_N_OFFSET(IPA_ENDPOINT_COUNT - 1); |
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name = "maximal endpoint status"; |
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if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) |
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return false; |
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return true; |
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} |
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bool ipa_cmd_data_valid(struct ipa *ipa) |
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{ |
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if (!ipa_cmd_header_valid(ipa)) |
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return false; |
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if (!ipa_cmd_register_write_valid(ipa)) |
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return false; |
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return true; |
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} |
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#endif /* IPA_VALIDATE */ |
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int ipa_cmd_pool_init(struct gsi_channel *channel, u32 tre_max) |
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{ |
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struct gsi_trans_info *trans_info = &channel->trans_info; |
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struct device *dev = channel->gsi->dev; |
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int ret; |
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/* This is as good a place as any to validate build constants */ |
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ipa_cmd_validate_build(); |
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/* Even though command payloads are allocated one at a time, |
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* a single transaction can require up to tlv_count of them, |
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* so we treat them as if that many can be allocated at once. |
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*/ |
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ret = gsi_trans_pool_init_dma(dev, &trans_info->cmd_pool, |
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sizeof(union ipa_cmd_payload), |
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tre_max, channel->tlv_count); |
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if (ret) |
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return ret; |
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/* Each TRE needs a command info structure */ |
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ret = gsi_trans_pool_init(&trans_info->info_pool, |
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sizeof(struct ipa_cmd_info), |
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tre_max, channel->tlv_count); |
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if (ret) |
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gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool); |
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return ret; |
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} |
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void ipa_cmd_pool_exit(struct gsi_channel *channel) |
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{ |
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struct gsi_trans_info *trans_info = &channel->trans_info; |
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struct device *dev = channel->gsi->dev; |
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gsi_trans_pool_exit(&trans_info->info_pool); |
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gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool); |
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} |
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static union ipa_cmd_payload * |
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ipa_cmd_payload_alloc(struct ipa *ipa, dma_addr_t *addr) |
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{ |
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struct gsi_trans_info *trans_info; |
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struct ipa_endpoint *endpoint; |
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endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; |
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trans_info = &ipa->gsi.channel[endpoint->channel_id].trans_info; |
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return gsi_trans_pool_alloc_dma(&trans_info->cmd_pool, addr); |
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} |
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/* If hash_size is 0, hash_offset and hash_addr ignored. */ |
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void ipa_cmd_table_init_add(struct gsi_trans *trans, |
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enum ipa_cmd_opcode opcode, u16 size, u32 offset, |
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dma_addr_t addr, u16 hash_size, u32 hash_offset, |
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dma_addr_t hash_addr) |
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{ |
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); |
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enum dma_data_direction direction = DMA_TO_DEVICE; |
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struct ipa_cmd_hw_ip_fltrt_init *payload; |
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union ipa_cmd_payload *cmd_payload; |
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dma_addr_t payload_addr; |
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u64 val; |
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/* Record the non-hash table offset and size */ |
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offset += ipa->mem_offset; |
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val = u64_encode_bits(offset, IP_FLTRT_FLAGS_NHASH_ADDR_FMASK); |
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val |= u64_encode_bits(size, IP_FLTRT_FLAGS_NHASH_SIZE_FMASK); |
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/* The hash table offset and address are zero if its size is 0 */ |
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if (hash_size) { |
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/* Record the hash table offset and size */ |
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hash_offset += ipa->mem_offset; |
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val |= u64_encode_bits(hash_offset, |
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IP_FLTRT_FLAGS_HASH_ADDR_FMASK); |
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val |= u64_encode_bits(hash_size, |
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IP_FLTRT_FLAGS_HASH_SIZE_FMASK); |
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} |
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cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); |
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payload = &cmd_payload->table_init; |
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/* Fill in all offsets and sizes and the non-hash table address */ |
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if (hash_size) |
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payload->hash_rules_addr = cpu_to_le64(hash_addr); |
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payload->flags = cpu_to_le64(val); |
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payload->nhash_rules_addr = cpu_to_le64(addr); |
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gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, |
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direction, opcode); |
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} |
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/* Initialize header space in IPA-local memory */ |
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void ipa_cmd_hdr_init_local_add(struct gsi_trans *trans, u32 offset, u16 size, |
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dma_addr_t addr) |
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{ |
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); |
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enum ipa_cmd_opcode opcode = IPA_CMD_HDR_INIT_LOCAL; |
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enum dma_data_direction direction = DMA_TO_DEVICE; |
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struct ipa_cmd_hw_hdr_init_local *payload; |
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union ipa_cmd_payload *cmd_payload; |
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dma_addr_t payload_addr; |
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u32 flags; |
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offset += ipa->mem_offset; |
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/* With this command we tell the IPA where in its local memory the |
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* header tables reside. The content of the buffer provided is |
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* also written via DMA into that space. The IPA hardware owns |
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* the table, but the AP must initialize it. |
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*/ |
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cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); |
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payload = &cmd_payload->hdr_init_local; |
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payload->hdr_table_addr = cpu_to_le64(addr); |
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flags = u32_encode_bits(size, HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK); |
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flags |= u32_encode_bits(offset, HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK); |
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payload->flags = cpu_to_le32(flags); |
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gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, |
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direction, opcode); |
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} |
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void ipa_cmd_register_write_add(struct gsi_trans *trans, u32 offset, u32 value, |
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u32 mask, bool clear_full) |
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{ |
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); |
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struct ipa_cmd_register_write *payload; |
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union ipa_cmd_payload *cmd_payload; |
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u32 opcode = IPA_CMD_REGISTER_WRITE; |
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dma_addr_t payload_addr; |
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u32 clear_option; |
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u32 options; |
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u16 flags; |
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/* pipeline_clear_src_grp is not used */ |
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clear_option = clear_full ? pipeline_clear_full : pipeline_clear_hps; |
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if (ipa->version != IPA_VERSION_3_5_1) { |
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u16 offset_high; |
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u32 val; |
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/* Opcode encodes pipeline clear options */ |
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/* SKIP_CLEAR is always 0 (don't skip pipeline clear) */ |
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val = u16_encode_bits(clear_option, |
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REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK); |
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opcode |= val; |
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/* Extract the high 4 bits from the offset */ |
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offset_high = (u16)u32_get_bits(offset, GENMASK(19, 16)); |
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offset &= (1 << 16) - 1; |
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/* Extract the top 4 bits and encode it into the flags field */ |
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flags = u16_encode_bits(offset_high, |
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REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK); |
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options = 0; /* reserved */ |
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} else { |
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flags = 0; /* SKIP_CLEAR flag is always 0 */ |
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options = u16_encode_bits(clear_option, |
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REGISTER_WRITE_CLEAR_OPTIONS_FMASK); |
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} |
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cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); |
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payload = &cmd_payload->register_write; |
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payload->flags = cpu_to_le16(flags); |
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payload->offset = cpu_to_le16((u16)offset); |
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payload->value = cpu_to_le32(value); |
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payload->value_mask = cpu_to_le32(mask); |
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payload->clear_options = cpu_to_le32(options); |
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gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, |
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DMA_NONE, opcode); |
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} |
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|
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/* Skip IP packet processing on the next data transfer on a TX channel */ |
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static void ipa_cmd_ip_packet_init_add(struct gsi_trans *trans, u8 endpoint_id) |
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{ |
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); |
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enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_INIT; |
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enum dma_data_direction direction = DMA_TO_DEVICE; |
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struct ipa_cmd_ip_packet_init *payload; |
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union ipa_cmd_payload *cmd_payload; |
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dma_addr_t payload_addr; |
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/* assert(endpoint_id < |
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field_max(IPA_PACKET_INIT_DEST_ENDPOINT_FMASK)); */ |
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cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); |
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payload = &cmd_payload->ip_packet_init; |
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payload->dest_endpoint = u8_encode_bits(endpoint_id, |
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IPA_PACKET_INIT_DEST_ENDPOINT_FMASK); |
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gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, |
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direction, opcode); |
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} |
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/* Use a DMA command to read or write a block of IPA-resident memory */ |
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void ipa_cmd_dma_shared_mem_add(struct gsi_trans *trans, u32 offset, u16 size, |
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dma_addr_t addr, bool toward_ipa) |
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{ |
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); |
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enum ipa_cmd_opcode opcode = IPA_CMD_DMA_SHARED_MEM; |
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struct ipa_cmd_hw_dma_mem_mem *payload; |
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union ipa_cmd_payload *cmd_payload; |
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enum dma_data_direction direction; |
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dma_addr_t payload_addr; |
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u16 flags; |
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/* size and offset must fit in 16 bit fields */ |
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/* assert(size > 0 && size <= U16_MAX); */ |
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/* assert(offset <= U16_MAX && ipa->mem_offset <= U16_MAX - offset); */ |
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offset += ipa->mem_offset; |
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cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); |
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payload = &cmd_payload->dma_shared_mem; |
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/* payload->clear_after_read was reserved prior to IPA v4.0. It's |
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* never needed for current code, so it's 0 regardless of version. |
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*/ |
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payload->size = cpu_to_le16(size); |
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payload->local_addr = cpu_to_le16(offset); |
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/* payload->flags: |
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* direction: 0 = write to IPA, 1 read from IPA |
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* Starting at v4.0 these are reserved; either way, all zero: |
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* pipeline clear: 0 = wait for pipeline clear (don't skip) |
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* clear_options: 0 = pipeline_clear_hps |
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* Instead, for v4.0+ these are encoded in the opcode. But again |
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* since both values are 0 we won't bother OR'ing them in. |
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*/ |
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flags = toward_ipa ? 0 : DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK; |
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payload->flags = cpu_to_le16(flags); |
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payload->system_addr = cpu_to_le64(addr); |
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direction = toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE; |
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gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, |
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direction, opcode); |
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} |
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static void ipa_cmd_ip_tag_status_add(struct gsi_trans *trans) |
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{ |
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); |
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enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_TAG_STATUS; |
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enum dma_data_direction direction = DMA_TO_DEVICE; |
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struct ipa_cmd_ip_packet_tag_status *payload; |
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union ipa_cmd_payload *cmd_payload; |
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dma_addr_t payload_addr; |
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/* assert(tag <= field_max(IP_PACKET_TAG_STATUS_TAG_FMASK)); */ |
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cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); |
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payload = &cmd_payload->ip_packet_tag_status; |
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payload->tag = le64_encode_bits(0, IP_PACKET_TAG_STATUS_TAG_FMASK); |
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gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, |
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direction, opcode); |
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} |
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/* Issue a small command TX data transfer */ |
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static void ipa_cmd_transfer_add(struct gsi_trans *trans) |
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{ |
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); |
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enum dma_data_direction direction = DMA_TO_DEVICE; |
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enum ipa_cmd_opcode opcode = IPA_CMD_NONE; |
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union ipa_cmd_payload *payload; |
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dma_addr_t payload_addr; |
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/* Just transfer a zero-filled payload structure */ |
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payload = ipa_cmd_payload_alloc(ipa, &payload_addr); |
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gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, |
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direction, opcode); |
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} |
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/* Add immediate commands to a transaction to clear the hardware pipeline */ |
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void ipa_cmd_pipeline_clear_add(struct gsi_trans *trans) |
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{ |
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struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); |
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struct ipa_endpoint *endpoint; |
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/* This will complete when the transfer is received */ |
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reinit_completion(&ipa->completion); |
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/* Issue a no-op register write command (mask 0 means no write) */ |
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ipa_cmd_register_write_add(trans, 0, 0, 0, true); |
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|
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/* Send a data packet through the IPA pipeline. The packet_init |
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* command says to send the next packet directly to the exception |
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* endpoint without any other IPA processing. The tag_status |
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* command requests that status be generated on completion of |
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* that transfer, and that it will be tagged with a value. |
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* Finally, the transfer command sends a small packet of data |
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* (instead of a command) using the command endpoint. |
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*/ |
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endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]; |
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ipa_cmd_ip_packet_init_add(trans, endpoint->endpoint_id); |
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ipa_cmd_ip_tag_status_add(trans); |
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ipa_cmd_transfer_add(trans); |
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} |
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/* Returns the number of commands required to clear the pipeline */ |
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u32 ipa_cmd_pipeline_clear_count(void) |
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{ |
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return 4; |
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} |
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void ipa_cmd_pipeline_clear_wait(struct ipa *ipa) |
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{ |
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wait_for_completion(&ipa->completion); |
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} |
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void ipa_cmd_pipeline_clear(struct ipa *ipa) |
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{ |
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u32 count = ipa_cmd_pipeline_clear_count(); |
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struct gsi_trans *trans; |
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|
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trans = ipa_cmd_trans_alloc(ipa, count); |
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if (trans) { |
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ipa_cmd_pipeline_clear_add(trans); |
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gsi_trans_commit_wait(trans); |
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ipa_cmd_pipeline_clear_wait(ipa); |
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} else { |
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dev_err(&ipa->pdev->dev, |
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"error allocating %u entry tag transaction\n", count); |
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} |
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} |
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static struct ipa_cmd_info * |
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ipa_cmd_info_alloc(struct ipa_endpoint *endpoint, u32 tre_count) |
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{ |
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struct gsi_channel *channel; |
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channel = &endpoint->ipa->gsi.channel[endpoint->channel_id]; |
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return gsi_trans_pool_alloc(&channel->trans_info.info_pool, tre_count); |
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} |
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/* Allocate a transaction for the command TX endpoint */ |
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struct gsi_trans *ipa_cmd_trans_alloc(struct ipa *ipa, u32 tre_count) |
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{ |
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struct ipa_endpoint *endpoint; |
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struct gsi_trans *trans; |
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endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; |
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trans = gsi_channel_trans_alloc(&ipa->gsi, endpoint->channel_id, |
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tre_count, DMA_NONE); |
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if (trans) |
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trans->info = ipa_cmd_info_alloc(endpoint, tre_count); |
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return trans; |
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}
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