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127 lines
2.9 KiB
127 lines
2.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* FUJITSU Extended Socket Network Device driver |
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* Copyright (c) 2015 FUJITSU LIMITED |
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*/ |
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#ifndef FJES_REGS_H_ |
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#define FJES_REGS_H_ |
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#include <linux/bitops.h> |
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#define XSCT_DEVICE_REGISTER_SIZE 0x1000 |
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/* register offset */ |
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/* Information registers */ |
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#define XSCT_OWNER_EPID 0x0000 /* Owner EPID */ |
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#define XSCT_MAX_EP 0x0004 /* Maximum EP */ |
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/* Device Control registers */ |
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#define XSCT_DCTL 0x0010 /* Device Control */ |
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/* Command Control registers */ |
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#define XSCT_CR 0x0020 /* Command request */ |
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#define XSCT_CS 0x0024 /* Command status */ |
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#define XSCT_SHSTSAL 0x0028 /* Share status address Low */ |
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#define XSCT_SHSTSAH 0x002C /* Share status address High */ |
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#define XSCT_REQBL 0x0034 /* Request Buffer length */ |
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#define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */ |
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#define XSCT_REQBAH 0x003C /* Request Buffer Address High */ |
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#define XSCT_RESPBL 0x0044 /* Response Buffer Length */ |
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#define XSCT_RESPBAL 0x0048 /* Response Buffer Address Low */ |
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#define XSCT_RESPBAH 0x004C /* Response Buffer Address High */ |
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/* Interrupt Control registers */ |
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#define XSCT_IS 0x0080 /* Interrupt status */ |
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#define XSCT_IMS 0x0084 /* Interrupt mask set */ |
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#define XSCT_IMC 0x0088 /* Interrupt mask clear */ |
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#define XSCT_IG 0x008C /* Interrupt generator */ |
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#define XSCT_ICTL 0x0090 /* Interrupt control */ |
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/* register structure */ |
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/* Information registers */ |
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union REG_OWNER_EPID { |
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struct { |
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__le32 epid:16; |
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__le32:16; |
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} bits; |
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__le32 reg; |
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}; |
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union REG_MAX_EP { |
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struct { |
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__le32 maxep:16; |
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__le32:16; |
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} bits; |
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__le32 reg; |
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}; |
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/* Device Control registers */ |
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union REG_DCTL { |
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struct { |
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__le32 reset:1; |
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__le32 rsv0:15; |
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__le32 rsv1:16; |
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} bits; |
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__le32 reg; |
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}; |
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/* Command Control registers */ |
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union REG_CR { |
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struct { |
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__le32 req_code:16; |
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__le32 err_info:14; |
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__le32 error:1; |
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__le32 req_start:1; |
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} bits; |
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__le32 reg; |
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}; |
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union REG_CS { |
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struct { |
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__le32 req_code:16; |
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__le32 rsv0:14; |
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__le32 busy:1; |
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__le32 complete:1; |
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} bits; |
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__le32 reg; |
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}; |
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/* Interrupt Control registers */ |
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union REG_ICTL { |
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struct { |
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__le32 automak:1; |
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__le32 rsv0:31; |
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} bits; |
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__le32 reg; |
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}; |
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enum REG_ICTL_MASK { |
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REG_ICTL_MASK_INFO_UPDATE = 1 << 20, |
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REG_ICTL_MASK_DEV_STOP_REQ = 1 << 19, |
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REG_ICTL_MASK_TXRX_STOP_REQ = 1 << 18, |
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REG_ICTL_MASK_TXRX_STOP_DONE = 1 << 17, |
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REG_ICTL_MASK_RX_DATA = 1 << 16, |
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REG_ICTL_MASK_ALL = GENMASK(20, 16), |
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}; |
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enum REG_IS_MASK { |
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REG_IS_MASK_IS_ASSERT = 1 << 31, |
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REG_IS_MASK_EPID = GENMASK(15, 0), |
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}; |
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struct fjes_hw; |
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u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg); |
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#define wr32(reg, val) \ |
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do { \ |
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u8 *base = hw->base; \ |
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writel((val), &base[(reg)]); \ |
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} while (0) |
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#define rd32(reg) (fjes_hw_rd32(hw, reg)) |
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#endif /* FJES_REGS_H_ */
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