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895 lines
29 KiB
895 lines
29 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (c) 2019, Vladimir Oltean <[email protected]> |
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*/ |
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#include "sja1105.h" |
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|
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#define SJA1105_TAS_CLKSRC_DISABLED 0 |
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#define SJA1105_TAS_CLKSRC_STANDALONE 1 |
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#define SJA1105_TAS_CLKSRC_AS6802 2 |
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#define SJA1105_TAS_CLKSRC_PTP 3 |
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#define SJA1105_GATE_MASK GENMASK_ULL(SJA1105_NUM_TC - 1, 0) |
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#define work_to_sja1105_tas(d) \ |
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container_of((d), struct sja1105_tas_data, tas_work) |
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#define tas_to_sja1105(d) \ |
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container_of((d), struct sja1105_private, tas_data) |
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|
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static int sja1105_tas_set_runtime_params(struct sja1105_private *priv) |
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{ |
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struct sja1105_tas_data *tas_data = &priv->tas_data; |
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struct sja1105_gating_config *gating_cfg = &tas_data->gating_cfg; |
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struct dsa_switch *ds = priv->ds; |
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s64 earliest_base_time = S64_MAX; |
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s64 latest_base_time = 0; |
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s64 its_cycle_time = 0; |
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s64 max_cycle_time = 0; |
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int port; |
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tas_data->enabled = false; |
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|
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for (port = 0; port < SJA1105_NUM_PORTS; port++) { |
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const struct tc_taprio_qopt_offload *offload; |
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|
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offload = tas_data->offload[port]; |
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if (!offload) |
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continue; |
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tas_data->enabled = true; |
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if (max_cycle_time < offload->cycle_time) |
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max_cycle_time = offload->cycle_time; |
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if (latest_base_time < offload->base_time) |
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latest_base_time = offload->base_time; |
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if (earliest_base_time > offload->base_time) { |
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earliest_base_time = offload->base_time; |
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its_cycle_time = offload->cycle_time; |
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} |
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} |
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if (!list_empty(&gating_cfg->entries)) { |
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tas_data->enabled = true; |
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if (max_cycle_time < gating_cfg->cycle_time) |
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max_cycle_time = gating_cfg->cycle_time; |
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if (latest_base_time < gating_cfg->base_time) |
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latest_base_time = gating_cfg->base_time; |
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if (earliest_base_time > gating_cfg->base_time) { |
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earliest_base_time = gating_cfg->base_time; |
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its_cycle_time = gating_cfg->cycle_time; |
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} |
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} |
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if (!tas_data->enabled) |
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return 0; |
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|
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/* Roll the earliest base time over until it is in a comparable |
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* time base with the latest, then compare their deltas. |
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* We want to enforce that all ports' base times are within |
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* SJA1105_TAS_MAX_DELTA 200ns cycles of one another. |
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*/ |
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earliest_base_time = future_base_time(earliest_base_time, |
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its_cycle_time, |
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latest_base_time); |
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while (earliest_base_time > latest_base_time) |
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earliest_base_time -= its_cycle_time; |
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if (latest_base_time - earliest_base_time > |
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sja1105_delta_to_ns(SJA1105_TAS_MAX_DELTA)) { |
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dev_err(ds->dev, |
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"Base times too far apart: min %llu max %llu\n", |
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earliest_base_time, latest_base_time); |
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return -ERANGE; |
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} |
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tas_data->earliest_base_time = earliest_base_time; |
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tas_data->max_cycle_time = max_cycle_time; |
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dev_dbg(ds->dev, "earliest base time %lld ns\n", earliest_base_time); |
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dev_dbg(ds->dev, "latest base time %lld ns\n", latest_base_time); |
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dev_dbg(ds->dev, "longest cycle time %lld ns\n", max_cycle_time); |
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return 0; |
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} |
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/* Lo and behold: the egress scheduler from hell. |
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* |
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* At the hardware level, the Time-Aware Shaper holds a global linear arrray of |
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* all schedule entries for all ports. These are the Gate Control List (GCL) |
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* entries, let's call them "timeslots" for short. This linear array of |
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* timeslots is held in BLK_IDX_SCHEDULE. |
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* |
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* Then there are a maximum of 8 "execution threads" inside the switch, which |
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* iterate cyclically through the "schedule". Each "cycle" has an entry point |
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* and an exit point, both being timeslot indices in the schedule table. The |
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* hardware calls each cycle a "subschedule". |
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* |
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* Subschedule (cycle) i starts when |
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* ptpclkval >= ptpschtm + BLK_IDX_SCHEDULE_ENTRY_POINTS[i].delta. |
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* |
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* The hardware scheduler iterates BLK_IDX_SCHEDULE with a k ranging from |
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* k = BLK_IDX_SCHEDULE_ENTRY_POINTS[i].address to |
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* k = BLK_IDX_SCHEDULE_PARAMS.subscheind[i] |
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* |
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* For each schedule entry (timeslot) k, the engine executes the gate control |
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* list entry for the duration of BLK_IDX_SCHEDULE[k].delta. |
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* |
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* +---------+ |
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* | | BLK_IDX_SCHEDULE_ENTRY_POINTS_PARAMS |
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* +---------+ |
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* | |
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* +-----------------+ |
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* | .actsubsch |
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* BLK_IDX_SCHEDULE_ENTRY_POINTS v |
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* +-------+-------+ |
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* |cycle 0|cycle 1| |
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* +-------+-------+ |
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* | | | | |
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* +----------------+ | | +-------------------------------------+ |
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* | .subschindx | | .subschindx | |
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* | | +---------------+ | |
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* | .address | .address | | |
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* | | | | |
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* | | | | |
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* | BLK_IDX_SCHEDULE v v | |
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* | +-------+-------+-------+-------+-------+------+ | |
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* | |entry 0|entry 1|entry 2|entry 3|entry 4|entry5| | |
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* | +-------+-------+-------+-------+-------+------+ | |
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* | ^ ^ ^ ^ | |
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* | | | | | | |
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* | +-------------------------+ | | | | |
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* | | +-------------------------------+ | | | |
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* | | | +-------------------+ | | |
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* | | | | | | |
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* | +---------------------------------------------------------------+ | |
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* | |subscheind[0]<=subscheind[1]<=subscheind[2]<=...<=subscheind[7]| | |
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* | +---------------------------------------------------------------+ | |
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* | ^ ^ BLK_IDX_SCHEDULE_PARAMS | |
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* | | | | |
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* +--------+ +-------------------------------------------+ |
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* |
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* In the above picture there are two subschedules (cycles): |
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* |
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* - cycle 0: iterates the schedule table from 0 to 2 (and back) |
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* - cycle 1: iterates the schedule table from 3 to 5 (and back) |
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* |
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* All other possible execution threads must be marked as unused by making |
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* their "subschedule end index" (subscheind) equal to the last valid |
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* subschedule's end index (in this case 5). |
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*/ |
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int sja1105_init_scheduling(struct sja1105_private *priv) |
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{ |
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struct sja1105_schedule_entry_points_entry *schedule_entry_points; |
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struct sja1105_schedule_entry_points_params_entry |
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*schedule_entry_points_params; |
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struct sja1105_schedule_params_entry *schedule_params; |
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struct sja1105_tas_data *tas_data = &priv->tas_data; |
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struct sja1105_gating_config *gating_cfg = &tas_data->gating_cfg; |
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struct sja1105_schedule_entry *schedule; |
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struct sja1105_table *table; |
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int schedule_start_idx; |
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s64 entry_point_delta; |
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int schedule_end_idx; |
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int num_entries = 0; |
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int num_cycles = 0; |
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int cycle = 0; |
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int i, k = 0; |
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int port, rc; |
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rc = sja1105_tas_set_runtime_params(priv); |
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if (rc < 0) |
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return rc; |
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/* Discard previous Schedule Table */ |
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE]; |
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if (table->entry_count) { |
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kfree(table->entries); |
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table->entry_count = 0; |
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} |
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/* Discard previous Schedule Entry Points Parameters Table */ |
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_ENTRY_POINTS_PARAMS]; |
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if (table->entry_count) { |
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kfree(table->entries); |
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table->entry_count = 0; |
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} |
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/* Discard previous Schedule Parameters Table */ |
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_PARAMS]; |
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if (table->entry_count) { |
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kfree(table->entries); |
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table->entry_count = 0; |
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} |
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/* Discard previous Schedule Entry Points Table */ |
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_ENTRY_POINTS]; |
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if (table->entry_count) { |
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kfree(table->entries); |
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table->entry_count = 0; |
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} |
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|
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/* Figure out the dimensioning of the problem */ |
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for (port = 0; port < SJA1105_NUM_PORTS; port++) { |
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if (tas_data->offload[port]) { |
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num_entries += tas_data->offload[port]->num_entries; |
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num_cycles++; |
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} |
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} |
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if (!list_empty(&gating_cfg->entries)) { |
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num_entries += gating_cfg->num_entries; |
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num_cycles++; |
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} |
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/* Nothing to do */ |
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if (!num_cycles) |
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return 0; |
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/* Pre-allocate space in the static config tables */ |
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/* Schedule Table */ |
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE]; |
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table->entries = kcalloc(num_entries, table->ops->unpacked_entry_size, |
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GFP_KERNEL); |
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if (!table->entries) |
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return -ENOMEM; |
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table->entry_count = num_entries; |
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schedule = table->entries; |
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/* Schedule Points Parameters Table */ |
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_ENTRY_POINTS_PARAMS]; |
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table->entries = kcalloc(SJA1105_MAX_SCHEDULE_ENTRY_POINTS_PARAMS_COUNT, |
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table->ops->unpacked_entry_size, GFP_KERNEL); |
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if (!table->entries) |
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/* Previously allocated memory will be freed automatically in |
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* sja1105_static_config_free. This is true for all early |
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* returns below. |
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*/ |
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return -ENOMEM; |
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table->entry_count = SJA1105_MAX_SCHEDULE_ENTRY_POINTS_PARAMS_COUNT; |
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schedule_entry_points_params = table->entries; |
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|
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/* Schedule Parameters Table */ |
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_PARAMS]; |
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table->entries = kcalloc(SJA1105_MAX_SCHEDULE_PARAMS_COUNT, |
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table->ops->unpacked_entry_size, GFP_KERNEL); |
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if (!table->entries) |
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return -ENOMEM; |
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table->entry_count = SJA1105_MAX_SCHEDULE_PARAMS_COUNT; |
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schedule_params = table->entries; |
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/* Schedule Entry Points Table */ |
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_ENTRY_POINTS]; |
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table->entries = kcalloc(num_cycles, table->ops->unpacked_entry_size, |
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GFP_KERNEL); |
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if (!table->entries) |
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return -ENOMEM; |
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table->entry_count = num_cycles; |
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schedule_entry_points = table->entries; |
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/* Finally start populating the static config tables */ |
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schedule_entry_points_params->clksrc = SJA1105_TAS_CLKSRC_PTP; |
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schedule_entry_points_params->actsubsch = num_cycles - 1; |
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for (port = 0; port < SJA1105_NUM_PORTS; port++) { |
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const struct tc_taprio_qopt_offload *offload; |
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/* Relative base time */ |
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s64 rbt; |
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offload = tas_data->offload[port]; |
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if (!offload) |
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continue; |
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schedule_start_idx = k; |
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schedule_end_idx = k + offload->num_entries - 1; |
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/* This is the base time expressed as a number of TAS ticks |
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* relative to PTPSCHTM, which we'll (perhaps improperly) call |
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* the operational base time. |
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*/ |
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rbt = future_base_time(offload->base_time, |
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offload->cycle_time, |
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tas_data->earliest_base_time); |
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rbt -= tas_data->earliest_base_time; |
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/* UM10944.pdf 4.2.2. Schedule Entry Points table says that |
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* delta cannot be zero, which is shitty. Advance all relative |
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* base times by 1 TAS delta, so that even the earliest base |
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* time becomes 1 in relative terms. Then start the operational |
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* base time (PTPSCHTM) one TAS delta earlier than planned. |
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*/ |
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entry_point_delta = ns_to_sja1105_delta(rbt) + 1; |
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schedule_entry_points[cycle].subschindx = cycle; |
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schedule_entry_points[cycle].delta = entry_point_delta; |
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schedule_entry_points[cycle].address = schedule_start_idx; |
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/* The subschedule end indices need to be |
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* monotonically increasing. |
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*/ |
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for (i = cycle; i < 8; i++) |
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schedule_params->subscheind[i] = schedule_end_idx; |
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for (i = 0; i < offload->num_entries; i++, k++) { |
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s64 delta_ns = offload->entries[i].interval; |
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schedule[k].delta = ns_to_sja1105_delta(delta_ns); |
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schedule[k].destports = BIT(port); |
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schedule[k].resmedia_en = true; |
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schedule[k].resmedia = SJA1105_GATE_MASK & |
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~offload->entries[i].gate_mask; |
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} |
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cycle++; |
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} |
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if (!list_empty(&gating_cfg->entries)) { |
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struct sja1105_gate_entry *e; |
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/* Relative base time */ |
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s64 rbt; |
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schedule_start_idx = k; |
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schedule_end_idx = k + gating_cfg->num_entries - 1; |
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rbt = future_base_time(gating_cfg->base_time, |
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gating_cfg->cycle_time, |
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tas_data->earliest_base_time); |
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rbt -= tas_data->earliest_base_time; |
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entry_point_delta = ns_to_sja1105_delta(rbt) + 1; |
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schedule_entry_points[cycle].subschindx = cycle; |
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schedule_entry_points[cycle].delta = entry_point_delta; |
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schedule_entry_points[cycle].address = schedule_start_idx; |
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for (i = cycle; i < 8; i++) |
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schedule_params->subscheind[i] = schedule_end_idx; |
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list_for_each_entry(e, &gating_cfg->entries, list) { |
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schedule[k].delta = ns_to_sja1105_delta(e->interval); |
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schedule[k].destports = e->rule->vl.destports; |
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schedule[k].setvalid = true; |
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schedule[k].txen = true; |
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schedule[k].vlindex = e->rule->vl.sharindx; |
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schedule[k].winstindex = e->rule->vl.sharindx; |
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if (e->gate_state) /* Gate open */ |
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schedule[k].winst = true; |
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else /* Gate closed */ |
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schedule[k].winend = true; |
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k++; |
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} |
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} |
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|
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return 0; |
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} |
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|
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/* Be there 2 port subschedules, each executing an arbitrary number of gate |
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* open/close events cyclically. |
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* None of those gate events must ever occur at the exact same time, otherwise |
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* the switch is known to act in exotically strange ways. |
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* However the hardware doesn't bother performing these integrity checks. |
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* So here we are with the task of validating whether the new @admin offload |
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* has any conflict with the already established TAS configuration in |
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* tas_data->offload. We already know the other ports are in harmony with one |
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* another, otherwise we wouldn't have saved them. |
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* Each gate event executes periodically, with a period of @cycle_time and a |
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* phase given by its cycle's @base_time plus its offset within the cycle |
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* (which in turn is given by the length of the events prior to it). |
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* There are two aspects to possible collisions: |
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* - Collisions within one cycle's (actually the longest cycle's) time frame. |
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* For that, we need to compare the cartesian product of each possible |
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* occurrence of each event within one cycle time. |
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* - Collisions in the future. Events may not collide within one cycle time, |
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* but if two port schedules don't have the same periodicity (aka the cycle |
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* times aren't multiples of one another), they surely will some time in the |
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* future (actually they will collide an infinite amount of times). |
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*/ |
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static bool |
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sja1105_tas_check_conflicts(struct sja1105_private *priv, int port, |
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const struct tc_taprio_qopt_offload *admin) |
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{ |
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struct sja1105_tas_data *tas_data = &priv->tas_data; |
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const struct tc_taprio_qopt_offload *offload; |
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s64 max_cycle_time, min_cycle_time; |
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s64 delta1, delta2; |
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s64 rbt1, rbt2; |
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s64 stop_time; |
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s64 t1, t2; |
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int i, j; |
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s32 rem; |
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|
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offload = tas_data->offload[port]; |
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if (!offload) |
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return false; |
|
|
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/* Check if the two cycle times are multiples of one another. |
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* If they aren't, then they will surely collide. |
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*/ |
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max_cycle_time = max(offload->cycle_time, admin->cycle_time); |
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min_cycle_time = min(offload->cycle_time, admin->cycle_time); |
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div_s64_rem(max_cycle_time, min_cycle_time, &rem); |
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if (rem) |
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return true; |
|
|
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/* Calculate the "reduced" base time of each of the two cycles |
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* (transposed back as close to 0 as possible) by dividing to |
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* the cycle time. |
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*/ |
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div_s64_rem(offload->base_time, offload->cycle_time, &rem); |
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rbt1 = rem; |
|
|
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div_s64_rem(admin->base_time, admin->cycle_time, &rem); |
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rbt2 = rem; |
|
|
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stop_time = max_cycle_time + max(rbt1, rbt2); |
|
|
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/* delta1 is the relative base time of each GCL entry within |
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* the established ports' TAS config. |
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*/ |
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for (i = 0, delta1 = 0; |
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i < offload->num_entries; |
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delta1 += offload->entries[i].interval, i++) { |
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/* delta2 is the relative base time of each GCL entry |
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* within the newly added TAS config. |
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*/ |
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for (j = 0, delta2 = 0; |
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j < admin->num_entries; |
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delta2 += admin->entries[j].interval, j++) { |
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/* t1 follows all possible occurrences of the |
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* established ports' GCL entry i within the |
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* first cycle time. |
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*/ |
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for (t1 = rbt1 + delta1; |
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t1 <= stop_time; |
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t1 += offload->cycle_time) { |
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/* t2 follows all possible occurrences |
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* of the newly added GCL entry j |
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* within the first cycle time. |
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*/ |
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for (t2 = rbt2 + delta2; |
|
t2 <= stop_time; |
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t2 += admin->cycle_time) { |
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if (t1 == t2) { |
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dev_warn(priv->ds->dev, |
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"GCL entry %d collides with entry %d of port %d\n", |
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j, i, port); |
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return true; |
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} |
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} |
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} |
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} |
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} |
|
|
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return false; |
|
} |
|
|
|
/* Check the tc-taprio configuration on @port for conflicts with the tc-gate |
|
* global subschedule. If @port is -1, check it against all ports. |
|
* To reuse the sja1105_tas_check_conflicts logic without refactoring it, |
|
* convert the gating configuration to a dummy tc-taprio offload structure. |
|
*/ |
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bool sja1105_gating_check_conflicts(struct sja1105_private *priv, int port, |
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struct netlink_ext_ack *extack) |
|
{ |
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struct sja1105_gating_config *gating_cfg = &priv->tas_data.gating_cfg; |
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size_t num_entries = gating_cfg->num_entries; |
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struct tc_taprio_qopt_offload *dummy; |
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struct sja1105_gate_entry *e; |
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bool conflict; |
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int i = 0; |
|
|
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if (list_empty(&gating_cfg->entries)) |
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return false; |
|
|
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dummy = kzalloc(struct_size(dummy, entries, num_entries), GFP_KERNEL); |
|
if (!dummy) { |
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NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory"); |
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return true; |
|
} |
|
|
|
dummy->num_entries = num_entries; |
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dummy->base_time = gating_cfg->base_time; |
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dummy->cycle_time = gating_cfg->cycle_time; |
|
|
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list_for_each_entry(e, &gating_cfg->entries, list) |
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dummy->entries[i++].interval = e->interval; |
|
|
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if (port != -1) { |
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conflict = sja1105_tas_check_conflicts(priv, port, dummy); |
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} else { |
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for (port = 0; port < SJA1105_NUM_PORTS; port++) { |
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conflict = sja1105_tas_check_conflicts(priv, port, |
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dummy); |
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if (conflict) |
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break; |
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} |
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} |
|
|
|
kfree(dummy); |
|
|
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return conflict; |
|
} |
|
|
|
int sja1105_setup_tc_taprio(struct dsa_switch *ds, int port, |
|
struct tc_taprio_qopt_offload *admin) |
|
{ |
|
struct sja1105_private *priv = ds->priv; |
|
struct sja1105_tas_data *tas_data = &priv->tas_data; |
|
int other_port, rc, i; |
|
|
|
/* Can't change an already configured port (must delete qdisc first). |
|
* Can't delete the qdisc from an unconfigured port. |
|
*/ |
|
if (!!tas_data->offload[port] == admin->enable) |
|
return -EINVAL; |
|
|
|
if (!admin->enable) { |
|
taprio_offload_free(tas_data->offload[port]); |
|
tas_data->offload[port] = NULL; |
|
|
|
rc = sja1105_init_scheduling(priv); |
|
if (rc < 0) |
|
return rc; |
|
|
|
return sja1105_static_config_reload(priv, SJA1105_SCHEDULING); |
|
} |
|
|
|
/* The cycle time extension is the amount of time the last cycle from |
|
* the old OPER needs to be extended in order to phase-align with the |
|
* base time of the ADMIN when that becomes the new OPER. |
|
* But of course our switch needs to be reset to switch-over between |
|
* the ADMIN and the OPER configs - so much for a seamless transition. |
|
* So don't add insult over injury and just say we don't support cycle |
|
* time extension. |
|
*/ |
|
if (admin->cycle_time_extension) |
|
return -ENOTSUPP; |
|
|
|
for (i = 0; i < admin->num_entries; i++) { |
|
s64 delta_ns = admin->entries[i].interval; |
|
s64 delta_cycles = ns_to_sja1105_delta(delta_ns); |
|
bool too_long, too_short; |
|
|
|
too_long = (delta_cycles >= SJA1105_TAS_MAX_DELTA); |
|
too_short = (delta_cycles == 0); |
|
if (too_long || too_short) { |
|
dev_err(priv->ds->dev, |
|
"Interval %llu too %s for GCL entry %d\n", |
|
delta_ns, too_long ? "long" : "short", i); |
|
return -ERANGE; |
|
} |
|
} |
|
|
|
for (other_port = 0; other_port < SJA1105_NUM_PORTS; other_port++) { |
|
if (other_port == port) |
|
continue; |
|
|
|
if (sja1105_tas_check_conflicts(priv, other_port, admin)) |
|
return -ERANGE; |
|
} |
|
|
|
if (sja1105_gating_check_conflicts(priv, port, NULL)) { |
|
dev_err(ds->dev, "Conflict with tc-gate schedule\n"); |
|
return -ERANGE; |
|
} |
|
|
|
tas_data->offload[port] = taprio_offload_get(admin); |
|
|
|
rc = sja1105_init_scheduling(priv); |
|
if (rc < 0) |
|
return rc; |
|
|
|
return sja1105_static_config_reload(priv, SJA1105_SCHEDULING); |
|
} |
|
|
|
static int sja1105_tas_check_running(struct sja1105_private *priv) |
|
{ |
|
struct sja1105_tas_data *tas_data = &priv->tas_data; |
|
struct dsa_switch *ds = priv->ds; |
|
struct sja1105_ptp_cmd cmd = {0}; |
|
int rc; |
|
|
|
rc = sja1105_ptp_commit(ds, &cmd, SPI_READ); |
|
if (rc < 0) |
|
return rc; |
|
|
|
if (cmd.ptpstrtsch == 1) |
|
/* Schedule successfully started */ |
|
tas_data->state = SJA1105_TAS_STATE_RUNNING; |
|
else if (cmd.ptpstopsch == 1) |
|
/* Schedule is stopped */ |
|
tas_data->state = SJA1105_TAS_STATE_DISABLED; |
|
else |
|
/* Schedule is probably not configured with PTP clock source */ |
|
rc = -EINVAL; |
|
|
|
return rc; |
|
} |
|
|
|
/* Write to PTPCLKCORP */ |
|
static int sja1105_tas_adjust_drift(struct sja1105_private *priv, |
|
u64 correction) |
|
{ |
|
const struct sja1105_regs *regs = priv->info->regs; |
|
u32 ptpclkcorp = ns_to_sja1105_ticks(correction); |
|
|
|
return sja1105_xfer_u32(priv, SPI_WRITE, regs->ptpclkcorp, |
|
&ptpclkcorp, NULL); |
|
} |
|
|
|
/* Write to PTPSCHTM */ |
|
static int sja1105_tas_set_base_time(struct sja1105_private *priv, |
|
u64 base_time) |
|
{ |
|
const struct sja1105_regs *regs = priv->info->regs; |
|
u64 ptpschtm = ns_to_sja1105_ticks(base_time); |
|
|
|
return sja1105_xfer_u64(priv, SPI_WRITE, regs->ptpschtm, |
|
&ptpschtm, NULL); |
|
} |
|
|
|
static int sja1105_tas_start(struct sja1105_private *priv) |
|
{ |
|
struct sja1105_tas_data *tas_data = &priv->tas_data; |
|
struct sja1105_ptp_cmd *cmd = &priv->ptp_data.cmd; |
|
struct dsa_switch *ds = priv->ds; |
|
int rc; |
|
|
|
dev_dbg(ds->dev, "Starting the TAS\n"); |
|
|
|
if (tas_data->state == SJA1105_TAS_STATE_ENABLED_NOT_RUNNING || |
|
tas_data->state == SJA1105_TAS_STATE_RUNNING) { |
|
dev_err(ds->dev, "TAS already started\n"); |
|
return -EINVAL; |
|
} |
|
|
|
cmd->ptpstrtsch = 1; |
|
cmd->ptpstopsch = 0; |
|
|
|
rc = sja1105_ptp_commit(ds, cmd, SPI_WRITE); |
|
if (rc < 0) |
|
return rc; |
|
|
|
tas_data->state = SJA1105_TAS_STATE_ENABLED_NOT_RUNNING; |
|
|
|
return 0; |
|
} |
|
|
|
static int sja1105_tas_stop(struct sja1105_private *priv) |
|
{ |
|
struct sja1105_tas_data *tas_data = &priv->tas_data; |
|
struct sja1105_ptp_cmd *cmd = &priv->ptp_data.cmd; |
|
struct dsa_switch *ds = priv->ds; |
|
int rc; |
|
|
|
dev_dbg(ds->dev, "Stopping the TAS\n"); |
|
|
|
if (tas_data->state == SJA1105_TAS_STATE_DISABLED) { |
|
dev_err(ds->dev, "TAS already disabled\n"); |
|
return -EINVAL; |
|
} |
|
|
|
cmd->ptpstopsch = 1; |
|
cmd->ptpstrtsch = 0; |
|
|
|
rc = sja1105_ptp_commit(ds, cmd, SPI_WRITE); |
|
if (rc < 0) |
|
return rc; |
|
|
|
tas_data->state = SJA1105_TAS_STATE_DISABLED; |
|
|
|
return 0; |
|
} |
|
|
|
/* The schedule engine and the PTP clock are driven by the same oscillator, and |
|
* they run in parallel. But whilst the PTP clock can keep an absolute |
|
* time-of-day, the schedule engine is only running in 'ticks' (25 ticks make |
|
* up a delta, which is 200ns), and wrapping around at the end of each cycle. |
|
* The schedule engine is started when the PTP clock reaches the PTPSCHTM time |
|
* (in PTP domain). |
|
* Because the PTP clock can be rate-corrected (accelerated or slowed down) by |
|
* a software servo, and the schedule engine clock runs in parallel to the PTP |
|
* clock, there is logic internal to the switch that periodically keeps the |
|
* schedule engine from drifting away. The frequency with which this internal |
|
* syntonization happens is the PTP clock correction period (PTPCLKCORP). It is |
|
* a value also in the PTP clock domain, and is also rate-corrected. |
|
* To be precise, during a correction period, there is logic to determine by |
|
* how many scheduler clock ticks has the PTP clock drifted. At the end of each |
|
* correction period/beginning of new one, the length of a delta is shrunk or |
|
* expanded with an integer number of ticks, compared with the typical 25. |
|
* So a delta lasts for 200ns (or 25 ticks) only on average. |
|
* Sometimes it is longer, sometimes it is shorter. The internal syntonization |
|
* logic can adjust for at most 5 ticks each 20 ticks. |
|
* |
|
* The first implication is that you should choose your schedule correction |
|
* period to be an integer multiple of the schedule length. Preferably one. |
|
* In case there are schedules of multiple ports active, then the correction |
|
* period needs to be a multiple of them all. Given the restriction that the |
|
* cycle times have to be multiples of one another anyway, this means the |
|
* correction period can simply be the largest cycle time, hence the current |
|
* choice. This way, the updates are always synchronous to the transmission |
|
* cycle, and therefore predictable. |
|
* |
|
* The second implication is that at the beginning of a correction period, the |
|
* first few deltas will be modulated in time, until the schedule engine is |
|
* properly phase-aligned with the PTP clock. For this reason, you should place |
|
* your best-effort traffic at the beginning of a cycle, and your |
|
* time-triggered traffic afterwards. |
|
* |
|
* The third implication is that once the schedule engine is started, it can |
|
* only adjust for so much drift within a correction period. In the servo you |
|
* can only change the PTPCLKRATE, but not step the clock (PTPCLKADD). If you |
|
* want to do the latter, you need to stop and restart the schedule engine, |
|
* which is what the state machine handles. |
|
*/ |
|
static void sja1105_tas_state_machine(struct work_struct *work) |
|
{ |
|
struct sja1105_tas_data *tas_data = work_to_sja1105_tas(work); |
|
struct sja1105_private *priv = tas_to_sja1105(tas_data); |
|
struct sja1105_ptp_data *ptp_data = &priv->ptp_data; |
|
struct timespec64 base_time_ts, now_ts; |
|
struct dsa_switch *ds = priv->ds; |
|
struct timespec64 diff; |
|
s64 base_time, now; |
|
int rc = 0; |
|
|
|
mutex_lock(&ptp_data->lock); |
|
|
|
switch (tas_data->state) { |
|
case SJA1105_TAS_STATE_DISABLED: |
|
/* Can't do anything at all if clock is still being stepped */ |
|
if (tas_data->last_op != SJA1105_PTP_ADJUSTFREQ) |
|
break; |
|
|
|
rc = sja1105_tas_adjust_drift(priv, tas_data->max_cycle_time); |
|
if (rc < 0) |
|
break; |
|
|
|
rc = __sja1105_ptp_gettimex(ds, &now, NULL); |
|
if (rc < 0) |
|
break; |
|
|
|
/* Plan to start the earliest schedule first. The others |
|
* will be started in hardware, by way of their respective |
|
* entry points delta. |
|
* Try our best to avoid fringe cases (race condition between |
|
* ptpschtm and ptpstrtsch) by pushing the oper_base_time at |
|
* least one second in the future from now. This is not ideal, |
|
* but this only needs to buy us time until the |
|
* sja1105_tas_start command below gets executed. |
|
*/ |
|
base_time = future_base_time(tas_data->earliest_base_time, |
|
tas_data->max_cycle_time, |
|
now + 1ull * NSEC_PER_SEC); |
|
base_time -= sja1105_delta_to_ns(1); |
|
|
|
rc = sja1105_tas_set_base_time(priv, base_time); |
|
if (rc < 0) |
|
break; |
|
|
|
tas_data->oper_base_time = base_time; |
|
|
|
rc = sja1105_tas_start(priv); |
|
if (rc < 0) |
|
break; |
|
|
|
base_time_ts = ns_to_timespec64(base_time); |
|
now_ts = ns_to_timespec64(now); |
|
|
|
dev_dbg(ds->dev, "OPER base time %lld.%09ld (now %lld.%09ld)\n", |
|
base_time_ts.tv_sec, base_time_ts.tv_nsec, |
|
now_ts.tv_sec, now_ts.tv_nsec); |
|
|
|
break; |
|
|
|
case SJA1105_TAS_STATE_ENABLED_NOT_RUNNING: |
|
if (tas_data->last_op != SJA1105_PTP_ADJUSTFREQ) { |
|
/* Clock was stepped.. bad news for TAS */ |
|
sja1105_tas_stop(priv); |
|
break; |
|
} |
|
|
|
/* Check if TAS has actually started, by comparing the |
|
* scheduled start time with the SJA1105 PTP clock |
|
*/ |
|
rc = __sja1105_ptp_gettimex(ds, &now, NULL); |
|
if (rc < 0) |
|
break; |
|
|
|
if (now < tas_data->oper_base_time) { |
|
/* TAS has not started yet */ |
|
diff = ns_to_timespec64(tas_data->oper_base_time - now); |
|
dev_dbg(ds->dev, "time to start: [%lld.%09ld]", |
|
diff.tv_sec, diff.tv_nsec); |
|
break; |
|
} |
|
|
|
/* Time elapsed, what happened? */ |
|
rc = sja1105_tas_check_running(priv); |
|
if (rc < 0) |
|
break; |
|
|
|
if (tas_data->state != SJA1105_TAS_STATE_RUNNING) |
|
/* TAS has started */ |
|
dev_err(ds->dev, |
|
"TAS not started despite time elapsed\n"); |
|
|
|
break; |
|
|
|
case SJA1105_TAS_STATE_RUNNING: |
|
/* Clock was stepped.. bad news for TAS */ |
|
if (tas_data->last_op != SJA1105_PTP_ADJUSTFREQ) { |
|
sja1105_tas_stop(priv); |
|
break; |
|
} |
|
|
|
rc = sja1105_tas_check_running(priv); |
|
if (rc < 0) |
|
break; |
|
|
|
if (tas_data->state != SJA1105_TAS_STATE_RUNNING) |
|
dev_err(ds->dev, "TAS surprisingly stopped\n"); |
|
|
|
break; |
|
|
|
default: |
|
if (net_ratelimit()) |
|
dev_err(ds->dev, "TAS in an invalid state (incorrect use of API)!\n"); |
|
} |
|
|
|
if (rc && net_ratelimit()) |
|
dev_err(ds->dev, "An operation returned %d\n", rc); |
|
|
|
mutex_unlock(&ptp_data->lock); |
|
} |
|
|
|
void sja1105_tas_clockstep(struct dsa_switch *ds) |
|
{ |
|
struct sja1105_private *priv = ds->priv; |
|
struct sja1105_tas_data *tas_data = &priv->tas_data; |
|
|
|
if (!tas_data->enabled) |
|
return; |
|
|
|
tas_data->last_op = SJA1105_PTP_CLOCKSTEP; |
|
schedule_work(&tas_data->tas_work); |
|
} |
|
|
|
void sja1105_tas_adjfreq(struct dsa_switch *ds) |
|
{ |
|
struct sja1105_private *priv = ds->priv; |
|
struct sja1105_tas_data *tas_data = &priv->tas_data; |
|
|
|
if (!tas_data->enabled) |
|
return; |
|
|
|
/* No reason to schedule the workqueue, nothing changed */ |
|
if (tas_data->state == SJA1105_TAS_STATE_RUNNING) |
|
return; |
|
|
|
tas_data->last_op = SJA1105_PTP_ADJUSTFREQ; |
|
schedule_work(&tas_data->tas_work); |
|
} |
|
|
|
void sja1105_tas_setup(struct dsa_switch *ds) |
|
{ |
|
struct sja1105_private *priv = ds->priv; |
|
struct sja1105_tas_data *tas_data = &priv->tas_data; |
|
|
|
INIT_WORK(&tas_data->tas_work, sja1105_tas_state_machine); |
|
tas_data->state = SJA1105_TAS_STATE_DISABLED; |
|
tas_data->last_op = SJA1105_PTP_NONE; |
|
|
|
INIT_LIST_HEAD(&tas_data->gating_cfg.entries); |
|
} |
|
|
|
void sja1105_tas_teardown(struct dsa_switch *ds) |
|
{ |
|
struct sja1105_private *priv = ds->priv; |
|
struct tc_taprio_qopt_offload *offload; |
|
int port; |
|
|
|
cancel_work_sync(&priv->tas_data.tas_work); |
|
|
|
for (port = 0; port < SJA1105_NUM_PORTS; port++) { |
|
offload = priv->tas_data.offload[port]; |
|
if (!offload) |
|
continue; |
|
|
|
taprio_offload_free(offload); |
|
} |
|
}
|
|
|