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315 lines
6.4 KiB
315 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* direct.c - Low-level direct PCI config space access |
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*/ |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/dmi.h> |
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#include <asm/pci_x86.h> |
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/* |
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* Functions for accessing PCI base (first 256 bytes) and extended |
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* (4096 bytes per PCI function) configuration space with type 1 |
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* accesses. |
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*/ |
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#define PCI_CONF1_ADDRESS(bus, devfn, reg) \ |
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(0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \ |
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| (devfn << 8) | (reg & 0xFC)) |
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static int pci_conf1_read(unsigned int seg, unsigned int bus, |
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unsigned int devfn, int reg, int len, u32 *value) |
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{ |
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unsigned long flags; |
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if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) { |
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*value = -1; |
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return -EINVAL; |
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} |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); |
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switch (len) { |
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case 1: |
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*value = inb(0xCFC + (reg & 3)); |
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break; |
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case 2: |
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*value = inw(0xCFC + (reg & 2)); |
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break; |
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case 4: |
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*value = inl(0xCFC); |
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break; |
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} |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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return 0; |
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} |
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static int pci_conf1_write(unsigned int seg, unsigned int bus, |
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unsigned int devfn, int reg, int len, u32 value) |
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{ |
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unsigned long flags; |
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if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) |
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return -EINVAL; |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); |
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switch (len) { |
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case 1: |
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outb((u8)value, 0xCFC + (reg & 3)); |
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break; |
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case 2: |
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outw((u16)value, 0xCFC + (reg & 2)); |
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break; |
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case 4: |
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outl((u32)value, 0xCFC); |
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break; |
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} |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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return 0; |
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} |
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#undef PCI_CONF1_ADDRESS |
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const struct pci_raw_ops pci_direct_conf1 = { |
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.read = pci_conf1_read, |
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.write = pci_conf1_write, |
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}; |
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/* |
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* Functions for accessing PCI configuration space with type 2 accesses |
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*/ |
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#define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg) |
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static int pci_conf2_read(unsigned int seg, unsigned int bus, |
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unsigned int devfn, int reg, int len, u32 *value) |
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{ |
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unsigned long flags; |
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int dev, fn; |
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WARN_ON(seg); |
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if ((bus > 255) || (devfn > 255) || (reg > 255)) { |
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*value = -1; |
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return -EINVAL; |
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} |
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dev = PCI_SLOT(devfn); |
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fn = PCI_FUNC(devfn); |
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if (dev & 0x10) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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outb((u8)(0xF0 | (fn << 1)), 0xCF8); |
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outb((u8)bus, 0xCFA); |
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switch (len) { |
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case 1: |
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*value = inb(PCI_CONF2_ADDRESS(dev, reg)); |
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break; |
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case 2: |
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*value = inw(PCI_CONF2_ADDRESS(dev, reg)); |
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break; |
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case 4: |
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*value = inl(PCI_CONF2_ADDRESS(dev, reg)); |
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break; |
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} |
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outb(0, 0xCF8); |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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return 0; |
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} |
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static int pci_conf2_write(unsigned int seg, unsigned int bus, |
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unsigned int devfn, int reg, int len, u32 value) |
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{ |
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unsigned long flags; |
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int dev, fn; |
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WARN_ON(seg); |
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if ((bus > 255) || (devfn > 255) || (reg > 255)) |
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return -EINVAL; |
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dev = PCI_SLOT(devfn); |
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fn = PCI_FUNC(devfn); |
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if (dev & 0x10) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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outb((u8)(0xF0 | (fn << 1)), 0xCF8); |
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outb((u8)bus, 0xCFA); |
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switch (len) { |
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case 1: |
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outb((u8)value, PCI_CONF2_ADDRESS(dev, reg)); |
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break; |
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case 2: |
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outw((u16)value, PCI_CONF2_ADDRESS(dev, reg)); |
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break; |
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case 4: |
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outl((u32)value, PCI_CONF2_ADDRESS(dev, reg)); |
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break; |
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} |
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outb(0, 0xCF8); |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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return 0; |
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} |
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#undef PCI_CONF2_ADDRESS |
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static const struct pci_raw_ops pci_direct_conf2 = { |
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.read = pci_conf2_read, |
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.write = pci_conf2_write, |
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}; |
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/* |
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* Before we decide to use direct hardware access mechanisms, we try to do some |
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* trivial checks to ensure it at least _seems_ to be working -- we just test |
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* whether bus 00 contains a host bridge (this is similar to checking |
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* techniques used in XFree86, but ours should be more reliable since we |
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* attempt to make use of direct access hints provided by the PCI BIOS). |
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* |
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* This should be close to trivial, but it isn't, because there are buggy |
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* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. |
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*/ |
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static int __init pci_sanity_check(const struct pci_raw_ops *o) |
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{ |
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u32 x = 0; |
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int devfn; |
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if (pci_probe & PCI_NO_CHECKS) |
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return 1; |
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/* Assume Type 1 works for newer systems. |
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This handles machines that don't have anything on PCI Bus 0. */ |
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if (dmi_get_bios_year() >= 2001) |
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return 1; |
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for (devfn = 0; devfn < 0x100; devfn++) { |
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if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x)) |
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continue; |
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if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA) |
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return 1; |
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if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x)) |
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continue; |
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if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ) |
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return 1; |
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} |
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DBG(KERN_WARNING "PCI: Sanity check failed\n"); |
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return 0; |
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} |
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static int __init pci_check_type1(void) |
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{ |
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unsigned long flags; |
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unsigned int tmp; |
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int works = 0; |
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local_irq_save(flags); |
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outb(0x01, 0xCFB); |
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tmp = inl(0xCF8); |
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outl(0x80000000, 0xCF8); |
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if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) { |
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works = 1; |
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} |
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outl(tmp, 0xCF8); |
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local_irq_restore(flags); |
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return works; |
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} |
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static int __init pci_check_type2(void) |
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{ |
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unsigned long flags; |
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int works = 0; |
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local_irq_save(flags); |
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outb(0x00, 0xCFB); |
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outb(0x00, 0xCF8); |
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outb(0x00, 0xCFA); |
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if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && |
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pci_sanity_check(&pci_direct_conf2)) { |
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works = 1; |
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} |
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local_irq_restore(flags); |
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return works; |
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} |
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void __init pci_direct_init(int type) |
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{ |
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if (type == 0) |
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return; |
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printk(KERN_INFO "PCI: Using configuration type %d for base access\n", |
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type); |
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if (type == 1) { |
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raw_pci_ops = &pci_direct_conf1; |
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if (raw_pci_ext_ops) |
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return; |
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if (!(pci_probe & PCI_HAS_IO_ECS)) |
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return; |
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printk(KERN_INFO "PCI: Using configuration type 1 " |
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"for extended access\n"); |
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raw_pci_ext_ops = &pci_direct_conf1; |
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return; |
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} |
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raw_pci_ops = &pci_direct_conf2; |
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} |
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int __init pci_direct_probe(void) |
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{ |
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if ((pci_probe & PCI_PROBE_CONF1) == 0) |
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goto type2; |
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if (!request_region(0xCF8, 8, "PCI conf1")) |
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goto type2; |
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if (pci_check_type1()) { |
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raw_pci_ops = &pci_direct_conf1; |
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port_cf9_safe = true; |
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return 1; |
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} |
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release_region(0xCF8, 8); |
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type2: |
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if ((pci_probe & PCI_PROBE_CONF2) == 0) |
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return 0; |
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if (!request_region(0xCF8, 4, "PCI conf2")) |
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return 0; |
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if (!request_region(0xC000, 0x1000, "PCI conf2")) |
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goto fail2; |
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if (pci_check_type2()) { |
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raw_pci_ops = &pci_direct_conf2; |
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port_cf9_safe = true; |
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return 2; |
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} |
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release_region(0xC000, 0x1000); |
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fail2: |
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release_region(0xCF8, 4); |
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return 0; |
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}
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