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407 lines
9.3 KiB
407 lines
9.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __KVM_X86_VMX_CAPS_H |
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#define __KVM_X86_VMX_CAPS_H |
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#include <asm/vmx.h> |
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#include "lapic.h" |
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extern bool __read_mostly enable_vpid; |
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extern bool __read_mostly flexpriority_enabled; |
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extern bool __read_mostly enable_ept; |
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extern bool __read_mostly enable_unrestricted_guest; |
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extern bool __read_mostly enable_ept_ad_bits; |
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extern bool __read_mostly enable_pml; |
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extern bool __read_mostly enable_apicv; |
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extern int __read_mostly pt_mode; |
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#define PT_MODE_SYSTEM 0 |
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#define PT_MODE_HOST_GUEST 1 |
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#define PMU_CAP_FW_WRITES (1ULL << 13) |
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#define PMU_CAP_LBR_FMT 0x3f |
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#define DEBUGCTLMSR_LBR_MASK (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) |
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struct nested_vmx_msrs { |
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/* |
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* We only store the "true" versions of the VMX capability MSRs. We |
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* generate the "non-true" versions by setting the must-be-1 bits |
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* according to the SDM. |
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*/ |
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u32 procbased_ctls_low; |
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u32 procbased_ctls_high; |
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u32 secondary_ctls_low; |
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u32 secondary_ctls_high; |
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u32 pinbased_ctls_low; |
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u32 pinbased_ctls_high; |
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u32 exit_ctls_low; |
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u32 exit_ctls_high; |
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u32 entry_ctls_low; |
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u32 entry_ctls_high; |
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u32 misc_low; |
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u32 misc_high; |
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u32 ept_caps; |
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u32 vpid_caps; |
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u64 basic; |
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u64 cr0_fixed0; |
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u64 cr0_fixed1; |
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u64 cr4_fixed0; |
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u64 cr4_fixed1; |
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u64 vmcs_enum; |
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u64 vmfunc_controls; |
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}; |
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struct vmcs_config { |
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int size; |
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int order; |
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u32 basic_cap; |
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u32 revision_id; |
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u32 pin_based_exec_ctrl; |
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u32 cpu_based_exec_ctrl; |
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u32 cpu_based_2nd_exec_ctrl; |
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u32 vmexit_ctrl; |
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u32 vmentry_ctrl; |
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struct nested_vmx_msrs nested; |
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}; |
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extern struct vmcs_config vmcs_config; |
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struct vmx_capability { |
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u32 ept; |
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u32 vpid; |
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}; |
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extern struct vmx_capability vmx_capability; |
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static inline bool cpu_has_vmx_basic_inout(void) |
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{ |
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return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); |
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} |
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static inline bool cpu_has_virtual_nmis(void) |
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{ |
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return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; |
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} |
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static inline bool cpu_has_vmx_preemption_timer(void) |
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{ |
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return vmcs_config.pin_based_exec_ctrl & |
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PIN_BASED_VMX_PREEMPTION_TIMER; |
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} |
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static inline bool cpu_has_vmx_posted_intr(void) |
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{ |
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return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
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vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; |
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} |
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static inline bool cpu_has_load_ia32_efer(void) |
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{ |
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return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER) && |
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(vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_EFER); |
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} |
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static inline bool cpu_has_load_perf_global_ctrl(void) |
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{ |
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return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && |
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(vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); |
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} |
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static inline bool cpu_has_vmx_mpx(void) |
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{ |
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return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && |
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(vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); |
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} |
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static inline bool cpu_has_vmx_tpr_shadow(void) |
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{ |
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return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
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} |
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static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
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{ |
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return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
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} |
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static inline bool cpu_has_vmx_msr_bitmap(void) |
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{ |
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return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
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} |
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static inline bool cpu_has_secondary_exec_ctrls(void) |
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{ |
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return vmcs_config.cpu_based_exec_ctrl & |
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CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
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} |
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static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
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} |
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static inline bool cpu_has_vmx_ept(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_ENABLE_EPT; |
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} |
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static inline bool vmx_umip_emulated(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_DESC; |
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} |
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static inline bool cpu_has_vmx_rdtscp(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_ENABLE_RDTSCP; |
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} |
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static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
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} |
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static inline bool cpu_has_vmx_vpid(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_ENABLE_VPID; |
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} |
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static inline bool cpu_has_vmx_wbinvd_exit(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_WBINVD_EXITING; |
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} |
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static inline bool cpu_has_vmx_unrestricted_guest(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_UNRESTRICTED_GUEST; |
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} |
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static inline bool cpu_has_vmx_apic_register_virt(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_APIC_REGISTER_VIRT; |
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} |
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static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; |
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} |
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static inline bool cpu_has_vmx_ple(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_PAUSE_LOOP_EXITING; |
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} |
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static inline bool cpu_has_vmx_rdrand(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_RDRAND_EXITING; |
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} |
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static inline bool cpu_has_vmx_invpcid(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_ENABLE_INVPCID; |
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} |
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static inline bool cpu_has_vmx_vmfunc(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_ENABLE_VMFUNC; |
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} |
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static inline bool cpu_has_vmx_shadow_vmcs(void) |
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{ |
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u64 vmx_msr; |
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/* check if the cpu supports writing r/o exit information fields */ |
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rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); |
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if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) |
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return false; |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_SHADOW_VMCS; |
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} |
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static inline bool cpu_has_vmx_encls_vmexit(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_ENCLS_EXITING; |
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} |
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static inline bool cpu_has_vmx_rdseed(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_RDSEED_EXITING; |
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} |
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static inline bool cpu_has_vmx_pml(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; |
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} |
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static inline bool cpu_has_vmx_xsaves(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_XSAVES; |
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} |
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static inline bool cpu_has_vmx_waitpkg(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; |
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} |
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static inline bool cpu_has_vmx_tsc_scaling(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_TSC_SCALING; |
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} |
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static inline bool cpu_has_vmx_bus_lock_detection(void) |
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{ |
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return vmcs_config.cpu_based_2nd_exec_ctrl & |
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SECONDARY_EXEC_BUS_LOCK_DETECTION; |
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} |
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static inline bool cpu_has_vmx_apicv(void) |
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{ |
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return cpu_has_vmx_apic_register_virt() && |
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cpu_has_vmx_virtual_intr_delivery() && |
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cpu_has_vmx_posted_intr(); |
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} |
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static inline bool cpu_has_vmx_flexpriority(void) |
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{ |
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return cpu_has_vmx_tpr_shadow() && |
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cpu_has_vmx_virtualize_apic_accesses(); |
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} |
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static inline bool cpu_has_vmx_ept_execute_only(void) |
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{ |
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return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
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} |
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static inline bool cpu_has_vmx_ept_4levels(void) |
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{ |
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return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; |
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} |
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static inline bool cpu_has_vmx_ept_5levels(void) |
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{ |
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return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; |
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} |
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static inline bool cpu_has_vmx_ept_mt_wb(void) |
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{ |
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return vmx_capability.ept & VMX_EPTP_WB_BIT; |
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} |
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static inline bool cpu_has_vmx_ept_2m_page(void) |
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{ |
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return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
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} |
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static inline bool cpu_has_vmx_ept_1g_page(void) |
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{ |
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return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
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} |
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static inline bool cpu_has_vmx_ept_ad_bits(void) |
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{ |
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return vmx_capability.ept & VMX_EPT_AD_BIT; |
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} |
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static inline bool cpu_has_vmx_invept_context(void) |
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{ |
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return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
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} |
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static inline bool cpu_has_vmx_invept_global(void) |
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{ |
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return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
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} |
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static inline bool cpu_has_vmx_invvpid(void) |
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{ |
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return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; |
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} |
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static inline bool cpu_has_vmx_invvpid_individual_addr(void) |
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{ |
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return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT; |
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} |
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static inline bool cpu_has_vmx_invvpid_single(void) |
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{ |
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return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; |
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} |
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static inline bool cpu_has_vmx_invvpid_global(void) |
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{ |
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return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; |
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} |
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static inline bool cpu_has_vmx_intel_pt(void) |
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{ |
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u64 vmx_msr; |
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rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); |
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return (vmx_msr & MSR_IA32_VMX_MISC_INTEL_PT) && |
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(vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) && |
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(vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_IA32_RTIT_CTL) && |
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(vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL); |
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} |
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/* |
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* Processor Trace can operate in one of three modes: |
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* a. system-wide: trace both host/guest and output to host buffer |
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* b. host-only: only trace host and output to host buffer |
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* c. host-guest: trace host and guest simultaneously and output to their |
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* respective buffer |
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* |
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* KVM currently only supports (a) and (c). |
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*/ |
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static inline bool vmx_pt_mode_is_system(void) |
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{ |
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return pt_mode == PT_MODE_SYSTEM; |
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} |
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static inline bool vmx_pt_mode_is_host_guest(void) |
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{ |
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return pt_mode == PT_MODE_HOST_GUEST; |
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} |
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static inline u64 vmx_get_perf_capabilities(void) |
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{ |
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u64 perf_cap = 0; |
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if (boot_cpu_has(X86_FEATURE_PDCM)) |
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rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap); |
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perf_cap &= PMU_CAP_LBR_FMT; |
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/* |
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* Since counters are virtualized, KVM would support full |
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* width counting unconditionally, even if the host lacks it. |
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*/ |
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return PMU_CAP_FW_WRITES | perf_cap; |
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} |
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static inline u64 vmx_supported_debugctl(void) |
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{ |
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u64 debugctl = 0; |
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if (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT) |
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debugctl |= DEBUGCTLMSR_LBR_MASK; |
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return debugctl; |
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} |
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#endif /* __KVM_X86_VMX_CAPS_H */
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