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556 lines
16 KiB
556 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Firmware replacement code. |
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* |
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* Work around broken BIOSes that don't set an aperture, only set the |
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* aperture in the AGP bridge, or set too small aperture. |
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* |
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* If all fails map the aperture over some low memory. This is cheaper than |
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* doing bounce buffering. The memory is lost. This is done at early boot |
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* because only the bootmem allocator can allocate 32+MB. |
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* |
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* Copyright 2002 Andi Kleen, SuSE Labs. |
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*/ |
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#define pr_fmt(fmt) "AGP: " fmt |
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|
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#include <linux/kernel.h> |
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#include <linux/kcore.h> |
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#include <linux/types.h> |
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#include <linux/init.h> |
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#include <linux/memblock.h> |
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#include <linux/mmzone.h> |
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#include <linux/pci_ids.h> |
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#include <linux/pci.h> |
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#include <linux/bitops.h> |
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#include <linux/suspend.h> |
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#include <asm/e820/api.h> |
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#include <asm/io.h> |
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#include <asm/iommu.h> |
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#include <asm/gart.h> |
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#include <asm/pci-direct.h> |
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#include <asm/dma.h> |
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#include <asm/amd_nb.h> |
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#include <asm/x86_init.h> |
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#include <linux/crash_dump.h> |
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|
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/* |
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* Using 512M as goal, in case kexec will load kernel_big |
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* that will do the on-position decompress, and could overlap with |
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* with the gart aperture that is used. |
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* Sequence: |
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* kernel_small |
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* ==> kexec (with kdump trigger path or gart still enabled) |
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* ==> kernel_small (gart area become e820_reserved) |
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* ==> kexec (with kdump trigger path or gart still enabled) |
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* ==> kerne_big (uncompressed size will be big than 64M or 128M) |
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* So don't use 512M below as gart iommu, leave the space for kernel |
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* code for safe. |
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*/ |
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#define GART_MIN_ADDR (512ULL << 20) |
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#define GART_MAX_ADDR (1ULL << 32) |
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|
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int gart_iommu_aperture; |
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int gart_iommu_aperture_disabled __initdata; |
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int gart_iommu_aperture_allowed __initdata; |
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|
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int fallback_aper_order __initdata = 1; /* 64MB */ |
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int fallback_aper_force __initdata; |
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|
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int fix_aperture __initdata = 1; |
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|
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#if defined(CONFIG_PROC_VMCORE) || defined(CONFIG_PROC_KCORE) |
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/* |
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* If the first kernel maps the aperture over e820 RAM, the kdump kernel will |
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* use the same range because it will remain configured in the northbridge. |
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* Trying to dump this area via /proc/vmcore may crash the machine, so exclude |
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* it from vmcore. |
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*/ |
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static unsigned long aperture_pfn_start, aperture_page_count; |
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|
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static int gart_mem_pfn_is_ram(unsigned long pfn) |
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{ |
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return likely((pfn < aperture_pfn_start) || |
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(pfn >= aperture_pfn_start + aperture_page_count)); |
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} |
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|
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static void __init exclude_from_core(u64 aper_base, u32 aper_order) |
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{ |
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aperture_pfn_start = aper_base >> PAGE_SHIFT; |
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aperture_page_count = (32 * 1024 * 1024) << aper_order >> PAGE_SHIFT; |
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#ifdef CONFIG_PROC_VMCORE |
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WARN_ON(register_oldmem_pfn_is_ram(&gart_mem_pfn_is_ram)); |
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#endif |
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#ifdef CONFIG_PROC_KCORE |
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WARN_ON(register_mem_pfn_is_ram(&gart_mem_pfn_is_ram)); |
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#endif |
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} |
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#else |
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static void exclude_from_core(u64 aper_base, u32 aper_order) |
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{ |
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} |
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#endif |
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|
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/* This code runs before the PCI subsystem is initialized, so just |
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access the northbridge directly. */ |
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|
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static u32 __init allocate_aperture(void) |
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{ |
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u32 aper_size; |
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unsigned long addr; |
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|
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/* aper_size should <= 1G */ |
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if (fallback_aper_order > 5) |
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fallback_aper_order = 5; |
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aper_size = (32 * 1024 * 1024) << fallback_aper_order; |
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|
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/* |
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* Aperture has to be naturally aligned. This means a 2GB aperture |
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* won't have much chance of finding a place in the lower 4GB of |
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* memory. Unfortunately we cannot move it up because that would |
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* make the IOMMU useless. |
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*/ |
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addr = memblock_find_in_range(GART_MIN_ADDR, GART_MAX_ADDR, |
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aper_size, aper_size); |
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if (!addr) { |
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pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n", |
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addr, addr + aper_size - 1, aper_size >> 10); |
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return 0; |
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} |
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memblock_reserve(addr, aper_size); |
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pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n", |
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addr, addr + aper_size - 1, aper_size >> 10); |
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register_nosave_region(addr >> PAGE_SHIFT, |
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(addr+aper_size) >> PAGE_SHIFT); |
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return (u32)addr; |
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} |
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/* Find a PCI capability */ |
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static u32 __init find_cap(int bus, int slot, int func, int cap) |
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{ |
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int bytes; |
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u8 pos; |
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if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & |
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PCI_STATUS_CAP_LIST)) |
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return 0; |
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pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); |
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for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { |
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u8 id; |
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pos &= ~3; |
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id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); |
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if (id == 0xff) |
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break; |
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if (id == cap) |
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return pos; |
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pos = read_pci_config_byte(bus, slot, func, |
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pos+PCI_CAP_LIST_NEXT); |
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} |
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return 0; |
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} |
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|
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/* Read a standard AGPv3 bridge header */ |
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static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) |
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{ |
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u32 apsize; |
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u32 apsizereg; |
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int nbits; |
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u32 aper_low, aper_hi; |
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u64 aper; |
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u32 old_order; |
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pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func); |
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apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14); |
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if (apsizereg == 0xffffffff) { |
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pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n", |
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bus, slot, func); |
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return 0; |
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} |
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/* old_order could be the value from NB gart setting */ |
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old_order = *order; |
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apsize = apsizereg & 0xfff; |
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/* Some BIOS use weird encodings not in the AGPv3 table. */ |
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if (apsize & 0xff) |
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apsize |= 0xf00; |
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nbits = hweight16(apsize); |
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*order = 7 - nbits; |
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if ((int)*order < 0) /* < 32MB */ |
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*order = 0; |
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aper_low = read_pci_config(bus, slot, func, 0x10); |
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aper_hi = read_pci_config(bus, slot, func, 0x14); |
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aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); |
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/* |
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* On some sick chips, APSIZE is 0. It means it wants 4G |
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* so let double check that order, and lets trust AMD NB settings: |
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*/ |
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pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n", |
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bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1, |
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32 << old_order); |
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if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) { |
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pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n", |
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bus, slot, func, 32 << *order, apsizereg); |
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*order = old_order; |
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} |
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pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n", |
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bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1, |
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32 << *order, apsizereg); |
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if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20)) |
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return 0; |
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return (u32)aper; |
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} |
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/* |
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* Look for an AGP bridge. Windows only expects the aperture in the |
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* AGP bridge and some BIOS forget to initialize the Northbridge too. |
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* Work around this here. |
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* |
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* Do an PCI bus scan by hand because we're running before the PCI |
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* subsystem. |
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* |
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* All AMD AGP bridges are AGPv3 compliant, so we can do this scan |
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* generically. It's probably overkill to always scan all slots because |
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* the AGP bridges should be always an own bus on the HT hierarchy, |
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* but do it here for future safety. |
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*/ |
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static u32 __init search_agp_bridge(u32 *order, int *valid_agp) |
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{ |
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int bus, slot, func; |
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|
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/* Poor man's PCI discovery */ |
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for (bus = 0; bus < 256; bus++) { |
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for (slot = 0; slot < 32; slot++) { |
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for (func = 0; func < 8; func++) { |
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u32 class, cap; |
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u8 type; |
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class = read_pci_config(bus, slot, func, |
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PCI_CLASS_REVISION); |
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if (class == 0xffffffff) |
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break; |
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switch (class >> 16) { |
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case PCI_CLASS_BRIDGE_HOST: |
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case PCI_CLASS_BRIDGE_OTHER: /* needed? */ |
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/* AGP bridge? */ |
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cap = find_cap(bus, slot, func, |
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PCI_CAP_ID_AGP); |
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if (!cap) |
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break; |
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*valid_agp = 1; |
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return read_agp(bus, slot, func, cap, |
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order); |
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} |
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/* No multi-function device? */ |
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type = read_pci_config_byte(bus, slot, func, |
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PCI_HEADER_TYPE); |
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if (!(type & 0x80)) |
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break; |
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} |
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} |
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} |
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pr_info("No AGP bridge found\n"); |
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return 0; |
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} |
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static bool gart_fix_e820 __initdata = true; |
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|
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static int __init parse_gart_mem(char *p) |
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{ |
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return kstrtobool(p, &gart_fix_e820); |
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} |
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early_param("gart_fix_e820", parse_gart_mem); |
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/* |
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* With kexec/kdump, if the first kernel doesn't shut down the GART and the |
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* second kernel allocates a different GART region, there might be two |
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* overlapping GART regions present: |
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* |
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* - the first still used by the GART initialized in the first kernel. |
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* - (sub-)set of it used as normal RAM by the second kernel. |
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* |
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* which leads to memory corruptions and a kernel panic eventually. |
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* |
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* This can also happen if the BIOS has forgotten to mark the GART region |
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* as reserved. |
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* |
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* Try to update the e820 map to mark that new region as reserved. |
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*/ |
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void __init early_gart_iommu_check(void) |
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{ |
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u32 agp_aper_order = 0; |
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int i, fix, slot, valid_agp = 0; |
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u32 ctl; |
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u32 aper_size = 0, aper_order = 0, last_aper_order = 0; |
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u64 aper_base = 0, last_aper_base = 0; |
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int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0; |
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if (!amd_gart_present()) |
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return; |
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if (!early_pci_allowed()) |
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return; |
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/* This is mostly duplicate of iommu_hole_init */ |
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search_agp_bridge(&agp_aper_order, &valid_agp); |
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fix = 0; |
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for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) { |
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int bus; |
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int dev_base, dev_limit; |
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bus = amd_nb_bus_dev_ranges[i].bus; |
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dev_base = amd_nb_bus_dev_ranges[i].dev_base; |
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dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; |
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for (slot = dev_base; slot < dev_limit; slot++) { |
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if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) |
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continue; |
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ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); |
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aper_enabled = ctl & GARTEN; |
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aper_order = (ctl >> 1) & 7; |
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aper_size = (32 * 1024 * 1024) << aper_order; |
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aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; |
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aper_base <<= 25; |
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if (last_valid) { |
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if ((aper_order != last_aper_order) || |
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(aper_base != last_aper_base) || |
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(aper_enabled != last_aper_enabled)) { |
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fix = 1; |
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break; |
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} |
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} |
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last_aper_order = aper_order; |
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last_aper_base = aper_base; |
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last_aper_enabled = aper_enabled; |
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last_valid = 1; |
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} |
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} |
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if (!fix && !aper_enabled) |
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return; |
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|
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if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) |
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fix = 1; |
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if (gart_fix_e820 && !fix && aper_enabled) { |
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if (e820__mapped_any(aper_base, aper_base + aper_size, |
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E820_TYPE_RAM)) { |
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/* reserve it, so we can reuse it in second kernel */ |
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pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n", |
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aper_base, aper_base + aper_size - 1); |
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e820__range_add(aper_base, aper_size, E820_TYPE_RESERVED); |
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e820__update_table_print(); |
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} |
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} |
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if (valid_agp) |
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return; |
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|
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/* disable them all at first */ |
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for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { |
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int bus; |
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int dev_base, dev_limit; |
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bus = amd_nb_bus_dev_ranges[i].bus; |
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dev_base = amd_nb_bus_dev_ranges[i].dev_base; |
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dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; |
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for (slot = dev_base; slot < dev_limit; slot++) { |
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if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) |
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continue; |
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ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); |
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ctl &= ~GARTEN; |
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); |
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} |
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} |
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} |
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static int __initdata printed_gart_size_msg; |
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int __init gart_iommu_hole_init(void) |
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{ |
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u32 agp_aper_base = 0, agp_aper_order = 0; |
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u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; |
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u64 aper_base, last_aper_base = 0; |
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int fix, slot, valid_agp = 0; |
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int i, node; |
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if (!amd_gart_present()) |
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return -ENODEV; |
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if (gart_iommu_aperture_disabled || !fix_aperture || |
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!early_pci_allowed()) |
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return -ENODEV; |
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pr_info("Checking aperture...\n"); |
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if (!fallback_aper_force) |
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agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp); |
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fix = 0; |
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node = 0; |
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for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { |
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int bus; |
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int dev_base, dev_limit; |
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u32 ctl; |
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bus = amd_nb_bus_dev_ranges[i].bus; |
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dev_base = amd_nb_bus_dev_ranges[i].dev_base; |
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dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; |
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for (slot = dev_base; slot < dev_limit; slot++) { |
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if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) |
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continue; |
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iommu_detected = 1; |
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gart_iommu_aperture = 1; |
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x86_init.iommu.iommu_init = gart_iommu_init; |
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|
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ctl = read_pci_config(bus, slot, 3, |
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AMD64_GARTAPERTURECTL); |
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|
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/* |
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* Before we do anything else disable the GART. It may |
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* still be enabled if we boot into a crash-kernel here. |
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* Reconfiguring the GART while it is enabled could have |
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* unknown side-effects. |
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*/ |
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ctl &= ~GARTEN; |
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write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); |
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|
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aper_order = (ctl >> 1) & 7; |
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aper_size = (32 * 1024 * 1024) << aper_order; |
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aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; |
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aper_base <<= 25; |
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pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n", |
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node, aper_base, aper_base + aper_size - 1, |
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aper_size >> 20); |
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node++; |
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|
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if (!aperture_valid(aper_base, aper_size, 64<<20)) { |
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if (valid_agp && agp_aper_base && |
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agp_aper_base == aper_base && |
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agp_aper_order == aper_order) { |
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/* the same between two setting from NB and agp */ |
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if (!no_iommu && |
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max_pfn > MAX_DMA32_PFN && |
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!printed_gart_size_msg) { |
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pr_err("you are using iommu with agp, but GART size is less than 64MB\n"); |
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pr_err("please increase GART size in your BIOS setup\n"); |
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pr_err("if BIOS doesn't have that option, contact your HW vendor!\n"); |
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printed_gart_size_msg = 1; |
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} |
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} else { |
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fix = 1; |
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goto out; |
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} |
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} |
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|
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if ((last_aper_order && aper_order != last_aper_order) || |
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(last_aper_base && aper_base != last_aper_base)) { |
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fix = 1; |
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goto out; |
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} |
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last_aper_order = aper_order; |
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last_aper_base = aper_base; |
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} |
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} |
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out: |
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if (!fix && !fallback_aper_force) { |
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if (last_aper_base) { |
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/* |
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* If this is the kdump kernel, the first kernel |
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* may have allocated the range over its e820 RAM |
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* and fixed up the northbridge |
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*/ |
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exclude_from_core(last_aper_base, last_aper_order); |
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|
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return 1; |
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} |
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return 0; |
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} |
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|
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if (!fallback_aper_force) { |
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aper_alloc = agp_aper_base; |
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aper_order = agp_aper_order; |
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} |
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if (aper_alloc) { |
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/* Got the aperture from the AGP bridge */ |
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} else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) || |
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force_iommu || |
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valid_agp || |
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fallback_aper_force) { |
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pr_info("Your BIOS doesn't leave an aperture memory hole\n"); |
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pr_info("Please enable the IOMMU option in the BIOS setup\n"); |
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pr_info("This costs you %dMB of RAM\n", |
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32 << fallback_aper_order); |
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|
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aper_order = fallback_aper_order; |
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aper_alloc = allocate_aperture(); |
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if (!aper_alloc) { |
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/* |
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* Could disable AGP and IOMMU here, but it's |
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* probably not worth it. But the later users |
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* cannot deal with bad apertures and turning |
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* on the aperture over memory causes very |
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* strange problems, so it's better to panic |
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* early. |
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*/ |
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panic("Not enough memory for aperture"); |
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} |
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} else { |
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return 0; |
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} |
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|
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/* |
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* If this is the kdump kernel _and_ the first kernel did not |
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* configure the aperture in the northbridge, this range may |
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* overlap with the first kernel's memory. We can't access the |
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* range through vmcore even though it should be part of the dump. |
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*/ |
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exclude_from_core(aper_alloc, aper_order); |
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|
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/* Fix up the north bridges */ |
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for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { |
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int bus, dev_base, dev_limit; |
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|
|
/* |
|
* Don't enable translation yet but enable GART IO and CPU |
|
* accesses and set DISTLBWALKPRB since GART table memory is UC. |
|
*/ |
|
u32 ctl = aper_order << 1; |
|
|
|
bus = amd_nb_bus_dev_ranges[i].bus; |
|
dev_base = amd_nb_bus_dev_ranges[i].dev_base; |
|
dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; |
|
for (slot = dev_base; slot < dev_limit; slot++) { |
|
if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) |
|
continue; |
|
|
|
write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); |
|
write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25); |
|
} |
|
} |
|
|
|
set_up_gart_resume(aper_order, aper_alloc); |
|
|
|
return 1; |
|
}
|
|
|