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804 lines
19 KiB
804 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_PARAVIRT_H |
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#define _ASM_X86_PARAVIRT_H |
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/* Various instructions on x86 need to be replaced for |
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* para-virtualization: those hooks are defined here. */ |
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|
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#ifdef CONFIG_PARAVIRT |
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#include <asm/pgtable_types.h> |
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#include <asm/asm.h> |
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#include <asm/nospec-branch.h> |
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#include <asm/paravirt_types.h> |
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#ifndef __ASSEMBLY__ |
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#include <linux/bug.h> |
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#include <linux/types.h> |
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#include <linux/cpumask.h> |
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#include <asm/frame.h> |
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static inline unsigned long long paravirt_sched_clock(void) |
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{ |
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return PVOP_CALL0(unsigned long long, time.sched_clock); |
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} |
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struct static_key; |
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extern struct static_key paravirt_steal_enabled; |
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extern struct static_key paravirt_steal_rq_enabled; |
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__visible void __native_queued_spin_unlock(struct qspinlock *lock); |
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bool pv_is_native_spin_unlock(void); |
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__visible bool __native_vcpu_is_preempted(long cpu); |
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bool pv_is_native_vcpu_is_preempted(void); |
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static inline u64 paravirt_steal_clock(int cpu) |
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{ |
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return PVOP_CALL1(u64, time.steal_clock, cpu); |
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} |
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/* The paravirtualized I/O functions */ |
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static inline void slow_down_io(void) |
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{ |
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pv_ops.cpu.io_delay(); |
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#ifdef REALLY_SLOW_IO |
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pv_ops.cpu.io_delay(); |
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pv_ops.cpu.io_delay(); |
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pv_ops.cpu.io_delay(); |
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#endif |
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} |
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void native_flush_tlb_local(void); |
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void native_flush_tlb_global(void); |
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void native_flush_tlb_one_user(unsigned long addr); |
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void native_flush_tlb_others(const struct cpumask *cpumask, |
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const struct flush_tlb_info *info); |
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static inline void __flush_tlb_local(void) |
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{ |
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PVOP_VCALL0(mmu.flush_tlb_user); |
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} |
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static inline void __flush_tlb_global(void) |
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{ |
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PVOP_VCALL0(mmu.flush_tlb_kernel); |
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} |
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static inline void __flush_tlb_one_user(unsigned long addr) |
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{ |
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PVOP_VCALL1(mmu.flush_tlb_one_user, addr); |
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} |
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static inline void __flush_tlb_others(const struct cpumask *cpumask, |
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const struct flush_tlb_info *info) |
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{ |
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PVOP_VCALL2(mmu.flush_tlb_others, cpumask, info); |
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} |
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static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) |
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{ |
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PVOP_VCALL2(mmu.tlb_remove_table, tlb, table); |
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} |
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static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) |
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{ |
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PVOP_VCALL1(mmu.exit_mmap, mm); |
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} |
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#ifdef CONFIG_PARAVIRT_XXL |
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static inline void load_sp0(unsigned long sp0) |
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{ |
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PVOP_VCALL1(cpu.load_sp0, sp0); |
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} |
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/* The paravirtualized CPUID instruction. */ |
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static inline void __cpuid(unsigned int *eax, unsigned int *ebx, |
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unsigned int *ecx, unsigned int *edx) |
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{ |
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PVOP_VCALL4(cpu.cpuid, eax, ebx, ecx, edx); |
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} |
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/* |
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* These special macros can be used to get or set a debugging register |
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*/ |
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static inline unsigned long paravirt_get_debugreg(int reg) |
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{ |
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return PVOP_CALL1(unsigned long, cpu.get_debugreg, reg); |
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} |
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#define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) |
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static inline void set_debugreg(unsigned long val, int reg) |
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{ |
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PVOP_VCALL2(cpu.set_debugreg, reg, val); |
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} |
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static inline unsigned long read_cr0(void) |
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{ |
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return PVOP_CALL0(unsigned long, cpu.read_cr0); |
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} |
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static inline void write_cr0(unsigned long x) |
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{ |
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PVOP_VCALL1(cpu.write_cr0, x); |
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} |
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static inline unsigned long read_cr2(void) |
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{ |
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return PVOP_CALLEE0(unsigned long, mmu.read_cr2); |
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} |
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static inline void write_cr2(unsigned long x) |
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{ |
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PVOP_VCALL1(mmu.write_cr2, x); |
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} |
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static inline unsigned long __read_cr3(void) |
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{ |
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return PVOP_CALL0(unsigned long, mmu.read_cr3); |
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} |
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static inline void write_cr3(unsigned long x) |
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{ |
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PVOP_VCALL1(mmu.write_cr3, x); |
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} |
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static inline void __write_cr4(unsigned long x) |
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{ |
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PVOP_VCALL1(cpu.write_cr4, x); |
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} |
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static inline void arch_safe_halt(void) |
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{ |
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PVOP_VCALL0(irq.safe_halt); |
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} |
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static inline void halt(void) |
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{ |
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PVOP_VCALL0(irq.halt); |
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} |
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static inline void wbinvd(void) |
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{ |
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PVOP_VCALL0(cpu.wbinvd); |
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} |
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static inline u64 paravirt_read_msr(unsigned msr) |
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{ |
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return PVOP_CALL1(u64, cpu.read_msr, msr); |
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} |
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static inline void paravirt_write_msr(unsigned msr, |
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unsigned low, unsigned high) |
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{ |
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PVOP_VCALL3(cpu.write_msr, msr, low, high); |
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} |
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static inline u64 paravirt_read_msr_safe(unsigned msr, int *err) |
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{ |
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return PVOP_CALL2(u64, cpu.read_msr_safe, msr, err); |
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} |
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static inline int paravirt_write_msr_safe(unsigned msr, |
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unsigned low, unsigned high) |
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{ |
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return PVOP_CALL3(int, cpu.write_msr_safe, msr, low, high); |
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} |
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#define rdmsr(msr, val1, val2) \ |
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do { \ |
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u64 _l = paravirt_read_msr(msr); \ |
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val1 = (u32)_l; \ |
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val2 = _l >> 32; \ |
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} while (0) |
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#define wrmsr(msr, val1, val2) \ |
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do { \ |
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paravirt_write_msr(msr, val1, val2); \ |
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} while (0) |
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#define rdmsrl(msr, val) \ |
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do { \ |
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val = paravirt_read_msr(msr); \ |
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} while (0) |
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static inline void wrmsrl(unsigned msr, u64 val) |
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{ |
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wrmsr(msr, (u32)val, (u32)(val>>32)); |
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} |
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#define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b) |
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/* rdmsr with exception handling */ |
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#define rdmsr_safe(msr, a, b) \ |
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({ \ |
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int _err; \ |
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u64 _l = paravirt_read_msr_safe(msr, &_err); \ |
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(*a) = (u32)_l; \ |
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(*b) = _l >> 32; \ |
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_err; \ |
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}) |
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static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
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{ |
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int err; |
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*p = paravirt_read_msr_safe(msr, &err); |
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return err; |
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} |
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static inline unsigned long long paravirt_read_pmc(int counter) |
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{ |
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return PVOP_CALL1(u64, cpu.read_pmc, counter); |
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} |
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#define rdpmc(counter, low, high) \ |
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do { \ |
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u64 _l = paravirt_read_pmc(counter); \ |
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low = (u32)_l; \ |
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high = _l >> 32; \ |
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} while (0) |
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#define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) |
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static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) |
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{ |
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PVOP_VCALL2(cpu.alloc_ldt, ldt, entries); |
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} |
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static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) |
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{ |
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PVOP_VCALL2(cpu.free_ldt, ldt, entries); |
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} |
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static inline void load_TR_desc(void) |
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{ |
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PVOP_VCALL0(cpu.load_tr_desc); |
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} |
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static inline void load_gdt(const struct desc_ptr *dtr) |
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{ |
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PVOP_VCALL1(cpu.load_gdt, dtr); |
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} |
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static inline void load_idt(const struct desc_ptr *dtr) |
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{ |
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PVOP_VCALL1(cpu.load_idt, dtr); |
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} |
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static inline void set_ldt(const void *addr, unsigned entries) |
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{ |
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PVOP_VCALL2(cpu.set_ldt, addr, entries); |
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} |
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static inline unsigned long paravirt_store_tr(void) |
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{ |
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return PVOP_CALL0(unsigned long, cpu.store_tr); |
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} |
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#define store_tr(tr) ((tr) = paravirt_store_tr()) |
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static inline void load_TLS(struct thread_struct *t, unsigned cpu) |
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{ |
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PVOP_VCALL2(cpu.load_tls, t, cpu); |
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} |
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static inline void load_gs_index(unsigned int gs) |
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{ |
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PVOP_VCALL1(cpu.load_gs_index, gs); |
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} |
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static inline void write_ldt_entry(struct desc_struct *dt, int entry, |
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const void *desc) |
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{ |
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PVOP_VCALL3(cpu.write_ldt_entry, dt, entry, desc); |
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} |
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static inline void write_gdt_entry(struct desc_struct *dt, int entry, |
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void *desc, int type) |
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{ |
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PVOP_VCALL4(cpu.write_gdt_entry, dt, entry, desc, type); |
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} |
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static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
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{ |
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PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g); |
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} |
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#ifdef CONFIG_X86_IOPL_IOPERM |
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static inline void tss_invalidate_io_bitmap(void) |
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{ |
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PVOP_VCALL0(cpu.invalidate_io_bitmap); |
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} |
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static inline void tss_update_io_bitmap(void) |
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{ |
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PVOP_VCALL0(cpu.update_io_bitmap); |
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} |
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#endif |
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static inline void paravirt_activate_mm(struct mm_struct *prev, |
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struct mm_struct *next) |
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{ |
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PVOP_VCALL2(mmu.activate_mm, prev, next); |
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} |
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static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, |
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struct mm_struct *mm) |
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{ |
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PVOP_VCALL2(mmu.dup_mmap, oldmm, mm); |
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} |
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static inline int paravirt_pgd_alloc(struct mm_struct *mm) |
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{ |
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return PVOP_CALL1(int, mmu.pgd_alloc, mm); |
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} |
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static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) |
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{ |
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PVOP_VCALL2(mmu.pgd_free, mm, pgd); |
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} |
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static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn) |
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{ |
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PVOP_VCALL2(mmu.alloc_pte, mm, pfn); |
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} |
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static inline void paravirt_release_pte(unsigned long pfn) |
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{ |
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PVOP_VCALL1(mmu.release_pte, pfn); |
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} |
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static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn) |
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{ |
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PVOP_VCALL2(mmu.alloc_pmd, mm, pfn); |
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} |
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static inline void paravirt_release_pmd(unsigned long pfn) |
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{ |
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PVOP_VCALL1(mmu.release_pmd, pfn); |
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} |
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static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn) |
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{ |
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PVOP_VCALL2(mmu.alloc_pud, mm, pfn); |
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} |
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static inline void paravirt_release_pud(unsigned long pfn) |
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{ |
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PVOP_VCALL1(mmu.release_pud, pfn); |
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} |
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static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn) |
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{ |
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PVOP_VCALL2(mmu.alloc_p4d, mm, pfn); |
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} |
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static inline void paravirt_release_p4d(unsigned long pfn) |
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{ |
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PVOP_VCALL1(mmu.release_p4d, pfn); |
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} |
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static inline pte_t __pte(pteval_t val) |
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{ |
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return (pte_t) { PVOP_CALLEE1(pteval_t, mmu.make_pte, val) }; |
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} |
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static inline pteval_t pte_val(pte_t pte) |
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{ |
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return PVOP_CALLEE1(pteval_t, mmu.pte_val, pte.pte); |
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} |
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static inline pgd_t __pgd(pgdval_t val) |
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{ |
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return (pgd_t) { PVOP_CALLEE1(pgdval_t, mmu.make_pgd, val) }; |
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} |
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static inline pgdval_t pgd_val(pgd_t pgd) |
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{ |
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return PVOP_CALLEE1(pgdval_t, mmu.pgd_val, pgd.pgd); |
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} |
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#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
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static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, |
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pte_t *ptep) |
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{ |
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pteval_t ret; |
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ret = PVOP_CALL3(pteval_t, mmu.ptep_modify_prot_start, vma, addr, ptep); |
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return (pte_t) { .pte = ret }; |
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} |
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static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, |
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pte_t *ptep, pte_t old_pte, pte_t pte) |
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{ |
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PVOP_VCALL4(mmu.ptep_modify_prot_commit, vma, addr, ptep, pte.pte); |
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} |
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static inline void set_pte(pte_t *ptep, pte_t pte) |
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{ |
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PVOP_VCALL2(mmu.set_pte, ptep, pte.pte); |
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} |
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static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
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{ |
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PVOP_VCALL2(mmu.set_pmd, pmdp, native_pmd_val(pmd)); |
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} |
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static inline pmd_t __pmd(pmdval_t val) |
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{ |
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return (pmd_t) { PVOP_CALLEE1(pmdval_t, mmu.make_pmd, val) }; |
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} |
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static inline pmdval_t pmd_val(pmd_t pmd) |
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{ |
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return PVOP_CALLEE1(pmdval_t, mmu.pmd_val, pmd.pmd); |
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} |
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static inline void set_pud(pud_t *pudp, pud_t pud) |
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{ |
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PVOP_VCALL2(mmu.set_pud, pudp, native_pud_val(pud)); |
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} |
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static inline pud_t __pud(pudval_t val) |
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{ |
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pudval_t ret; |
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ret = PVOP_CALLEE1(pudval_t, mmu.make_pud, val); |
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return (pud_t) { ret }; |
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} |
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static inline pudval_t pud_val(pud_t pud) |
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{ |
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return PVOP_CALLEE1(pudval_t, mmu.pud_val, pud.pud); |
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} |
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static inline void pud_clear(pud_t *pudp) |
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{ |
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set_pud(pudp, native_make_pud(0)); |
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} |
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static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) |
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{ |
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p4dval_t val = native_p4d_val(p4d); |
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PVOP_VCALL2(mmu.set_p4d, p4dp, val); |
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} |
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#if CONFIG_PGTABLE_LEVELS >= 5 |
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static inline p4d_t __p4d(p4dval_t val) |
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{ |
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p4dval_t ret = PVOP_CALLEE1(p4dval_t, mmu.make_p4d, val); |
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return (p4d_t) { ret }; |
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} |
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static inline p4dval_t p4d_val(p4d_t p4d) |
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{ |
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return PVOP_CALLEE1(p4dval_t, mmu.p4d_val, p4d.p4d); |
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} |
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static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd) |
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{ |
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PVOP_VCALL2(mmu.set_pgd, pgdp, native_pgd_val(pgd)); |
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} |
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#define set_pgd(pgdp, pgdval) do { \ |
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if (pgtable_l5_enabled()) \ |
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__set_pgd(pgdp, pgdval); \ |
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else \ |
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set_p4d((p4d_t *)(pgdp), (p4d_t) { (pgdval).pgd }); \ |
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} while (0) |
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#define pgd_clear(pgdp) do { \ |
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if (pgtable_l5_enabled()) \ |
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set_pgd(pgdp, native_make_pgd(0)); \ |
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} while (0) |
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#endif /* CONFIG_PGTABLE_LEVELS == 5 */ |
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static inline void p4d_clear(p4d_t *p4dp) |
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{ |
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set_p4d(p4dp, native_make_p4d(0)); |
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} |
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static inline void set_pte_atomic(pte_t *ptep, pte_t pte) |
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{ |
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set_pte(ptep, pte); |
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} |
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static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
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pte_t *ptep) |
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{ |
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set_pte(ptep, native_make_pte(0)); |
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} |
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static inline void pmd_clear(pmd_t *pmdp) |
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{ |
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set_pmd(pmdp, native_make_pmd(0)); |
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} |
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#define __HAVE_ARCH_START_CONTEXT_SWITCH |
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static inline void arch_start_context_switch(struct task_struct *prev) |
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{ |
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PVOP_VCALL1(cpu.start_context_switch, prev); |
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} |
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static inline void arch_end_context_switch(struct task_struct *next) |
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{ |
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PVOP_VCALL1(cpu.end_context_switch, next); |
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} |
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#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE |
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static inline void arch_enter_lazy_mmu_mode(void) |
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{ |
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PVOP_VCALL0(mmu.lazy_mode.enter); |
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} |
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static inline void arch_leave_lazy_mmu_mode(void) |
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{ |
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PVOP_VCALL0(mmu.lazy_mode.leave); |
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} |
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static inline void arch_flush_lazy_mmu_mode(void) |
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{ |
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PVOP_VCALL0(mmu.lazy_mode.flush); |
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} |
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static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, |
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phys_addr_t phys, pgprot_t flags) |
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{ |
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pv_ops.mmu.set_fixmap(idx, phys, flags); |
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} |
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#endif |
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#if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS) |
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static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock, |
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u32 val) |
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{ |
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PVOP_VCALL2(lock.queued_spin_lock_slowpath, lock, val); |
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} |
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static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock) |
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{ |
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PVOP_VCALLEE1(lock.queued_spin_unlock, lock); |
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} |
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static __always_inline void pv_wait(u8 *ptr, u8 val) |
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{ |
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PVOP_VCALL2(lock.wait, ptr, val); |
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} |
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static __always_inline void pv_kick(int cpu) |
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{ |
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PVOP_VCALL1(lock.kick, cpu); |
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} |
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static __always_inline bool pv_vcpu_is_preempted(long cpu) |
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{ |
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return PVOP_CALLEE1(bool, lock.vcpu_is_preempted, cpu); |
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} |
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void __raw_callee_save___native_queued_spin_unlock(struct qspinlock *lock); |
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bool __raw_callee_save___native_vcpu_is_preempted(long cpu); |
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#endif /* SMP && PARAVIRT_SPINLOCKS */ |
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#ifdef CONFIG_X86_32 |
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/* save and restore all caller-save registers, except return value */ |
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#define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" |
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#define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" |
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#else |
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/* save and restore all caller-save registers, except return value */ |
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#define PV_SAVE_ALL_CALLER_REGS \ |
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"push %rcx;" \ |
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"push %rdx;" \ |
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"push %rsi;" \ |
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"push %rdi;" \ |
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"push %r8;" \ |
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"push %r9;" \ |
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"push %r10;" \ |
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"push %r11;" |
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#define PV_RESTORE_ALL_CALLER_REGS \ |
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"pop %r11;" \ |
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"pop %r10;" \ |
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"pop %r9;" \ |
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"pop %r8;" \ |
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"pop %rdi;" \ |
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"pop %rsi;" \ |
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"pop %rdx;" \ |
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"pop %rcx;" |
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#endif |
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|
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/* |
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* Generate a thunk around a function which saves all caller-save |
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* registers except for the return value. This allows C functions to |
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* be called from assembler code where fewer than normal registers are |
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* available. It may also help code generation around calls from C |
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* code if the common case doesn't use many registers. |
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* |
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* When a callee is wrapped in a thunk, the caller can assume that all |
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* arg regs and all scratch registers are preserved across the |
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* call. The return value in rax/eax will not be saved, even for void |
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* functions. |
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*/ |
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#define PV_THUNK_NAME(func) "__raw_callee_save_" #func |
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#define PV_CALLEE_SAVE_REGS_THUNK(func) \ |
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extern typeof(func) __raw_callee_save_##func; \ |
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\ |
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asm(".pushsection .text;" \ |
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".globl " PV_THUNK_NAME(func) ";" \ |
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".type " PV_THUNK_NAME(func) ", @function;" \ |
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PV_THUNK_NAME(func) ":" \ |
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FRAME_BEGIN \ |
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PV_SAVE_ALL_CALLER_REGS \ |
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"call " #func ";" \ |
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PV_RESTORE_ALL_CALLER_REGS \ |
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FRAME_END \ |
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"ret;" \ |
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".size " PV_THUNK_NAME(func) ", .-" PV_THUNK_NAME(func) ";" \ |
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".popsection") |
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|
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/* Get a reference to a callee-save function */ |
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#define PV_CALLEE_SAVE(func) \ |
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((struct paravirt_callee_save) { __raw_callee_save_##func }) |
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|
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/* Promise that "func" already uses the right calling convention */ |
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#define __PV_IS_CALLEE_SAVE(func) \ |
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((struct paravirt_callee_save) { func }) |
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|
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#ifdef CONFIG_PARAVIRT_XXL |
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static inline notrace unsigned long arch_local_save_flags(void) |
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{ |
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return PVOP_CALLEE0(unsigned long, irq.save_fl); |
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} |
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|
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static inline notrace void arch_local_irq_disable(void) |
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{ |
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PVOP_VCALLEE0(irq.irq_disable); |
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} |
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|
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static inline notrace void arch_local_irq_enable(void) |
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{ |
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PVOP_VCALLEE0(irq.irq_enable); |
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} |
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|
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static inline notrace unsigned long arch_local_irq_save(void) |
|
{ |
|
unsigned long f; |
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|
|
f = arch_local_save_flags(); |
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arch_local_irq_disable(); |
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return f; |
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} |
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#endif |
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|
|
|
|
/* Make sure as little as possible of this mess escapes. */ |
|
#undef PARAVIRT_CALL |
|
#undef __PVOP_CALL |
|
#undef __PVOP_VCALL |
|
#undef PVOP_VCALL0 |
|
#undef PVOP_CALL0 |
|
#undef PVOP_VCALL1 |
|
#undef PVOP_CALL1 |
|
#undef PVOP_VCALL2 |
|
#undef PVOP_CALL2 |
|
#undef PVOP_VCALL3 |
|
#undef PVOP_CALL3 |
|
#undef PVOP_VCALL4 |
|
#undef PVOP_CALL4 |
|
|
|
extern void default_banner(void); |
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|
|
#else /* __ASSEMBLY__ */ |
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|
|
#define _PVSITE(ptype, ops, word, algn) \ |
|
771:; \ |
|
ops; \ |
|
772:; \ |
|
.pushsection .parainstructions,"a"; \ |
|
.align algn; \ |
|
word 771b; \ |
|
.byte ptype; \ |
|
.byte 772b-771b; \ |
|
.popsection |
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|
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|
|
#define COND_PUSH(set, mask, reg) \ |
|
.if ((~(set)) & mask); push %reg; .endif |
|
#define COND_POP(set, mask, reg) \ |
|
.if ((~(set)) & mask); pop %reg; .endif |
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|
|
#ifdef CONFIG_X86_64 |
|
|
|
#define PV_SAVE_REGS(set) \ |
|
COND_PUSH(set, CLBR_RAX, rax); \ |
|
COND_PUSH(set, CLBR_RCX, rcx); \ |
|
COND_PUSH(set, CLBR_RDX, rdx); \ |
|
COND_PUSH(set, CLBR_RSI, rsi); \ |
|
COND_PUSH(set, CLBR_RDI, rdi); \ |
|
COND_PUSH(set, CLBR_R8, r8); \ |
|
COND_PUSH(set, CLBR_R9, r9); \ |
|
COND_PUSH(set, CLBR_R10, r10); \ |
|
COND_PUSH(set, CLBR_R11, r11) |
|
#define PV_RESTORE_REGS(set) \ |
|
COND_POP(set, CLBR_R11, r11); \ |
|
COND_POP(set, CLBR_R10, r10); \ |
|
COND_POP(set, CLBR_R9, r9); \ |
|
COND_POP(set, CLBR_R8, r8); \ |
|
COND_POP(set, CLBR_RDI, rdi); \ |
|
COND_POP(set, CLBR_RSI, rsi); \ |
|
COND_POP(set, CLBR_RDX, rdx); \ |
|
COND_POP(set, CLBR_RCX, rcx); \ |
|
COND_POP(set, CLBR_RAX, rax) |
|
|
|
#define PARA_PATCH(off) ((off) / 8) |
|
#define PARA_SITE(ptype, ops) _PVSITE(ptype, ops, .quad, 8) |
|
#define PARA_INDIRECT(addr) *addr(%rip) |
|
#else |
|
#define PV_SAVE_REGS(set) \ |
|
COND_PUSH(set, CLBR_EAX, eax); \ |
|
COND_PUSH(set, CLBR_EDI, edi); \ |
|
COND_PUSH(set, CLBR_ECX, ecx); \ |
|
COND_PUSH(set, CLBR_EDX, edx) |
|
#define PV_RESTORE_REGS(set) \ |
|
COND_POP(set, CLBR_EDX, edx); \ |
|
COND_POP(set, CLBR_ECX, ecx); \ |
|
COND_POP(set, CLBR_EDI, edi); \ |
|
COND_POP(set, CLBR_EAX, eax) |
|
|
|
#define PARA_PATCH(off) ((off) / 4) |
|
#define PARA_SITE(ptype, ops) _PVSITE(ptype, ops, .long, 4) |
|
#define PARA_INDIRECT(addr) *%cs:addr |
|
#endif |
|
|
|
#ifdef CONFIG_PARAVIRT_XXL |
|
#define INTERRUPT_RETURN \ |
|
PARA_SITE(PARA_PATCH(PV_CPU_iret), \ |
|
ANNOTATE_RETPOLINE_SAFE; \ |
|
jmp PARA_INDIRECT(pv_ops+PV_CPU_iret);) |
|
|
|
#define DISABLE_INTERRUPTS(clobbers) \ |
|
PARA_SITE(PARA_PATCH(PV_IRQ_irq_disable), \ |
|
PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
|
ANNOTATE_RETPOLINE_SAFE; \ |
|
call PARA_INDIRECT(pv_ops+PV_IRQ_irq_disable); \ |
|
PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
|
|
|
#define ENABLE_INTERRUPTS(clobbers) \ |
|
PARA_SITE(PARA_PATCH(PV_IRQ_irq_enable), \ |
|
PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
|
ANNOTATE_RETPOLINE_SAFE; \ |
|
call PARA_INDIRECT(pv_ops+PV_IRQ_irq_enable); \ |
|
PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
|
#endif |
|
|
|
#ifdef CONFIG_X86_64 |
|
#ifdef CONFIG_PARAVIRT_XXL |
|
#ifdef CONFIG_DEBUG_ENTRY |
|
#define SAVE_FLAGS(clobbers) \ |
|
PARA_SITE(PARA_PATCH(PV_IRQ_save_fl), \ |
|
PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
|
ANNOTATE_RETPOLINE_SAFE; \ |
|
call PARA_INDIRECT(pv_ops+PV_IRQ_save_fl); \ |
|
PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
|
#endif |
|
#endif /* CONFIG_PARAVIRT_XXL */ |
|
#endif /* CONFIG_X86_64 */ |
|
|
|
#endif /* __ASSEMBLY__ */ |
|
#else /* CONFIG_PARAVIRT */ |
|
# define default_banner x86_init_noop |
|
#endif /* !CONFIG_PARAVIRT */ |
|
|
|
#ifndef __ASSEMBLY__ |
|
#ifndef CONFIG_PARAVIRT_XXL |
|
static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, |
|
struct mm_struct *mm) |
|
{ |
|
} |
|
#endif |
|
|
|
#ifndef CONFIG_PARAVIRT |
|
static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) |
|
{ |
|
} |
|
#endif |
|
#endif /* __ASSEMBLY__ */ |
|
#endif /* _ASM_X86_PARAVIRT_H */
|
|
|