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182 lines
4.2 KiB
182 lines
4.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_MPSPEC_DEF_H |
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#define _ASM_X86_MPSPEC_DEF_H |
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/* |
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* Structure definitions for SMP machines following the |
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* Intel Multiprocessing Specification 1.1 and 1.4. |
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*/ |
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/* |
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* This tag identifies where the SMP configuration |
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* information is. |
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*/ |
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#define SMP_MAGIC_IDENT (('_'<<24) | ('P'<<16) | ('M'<<8) | '_') |
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#ifdef CONFIG_X86_32 |
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# define MAX_MPC_ENTRY 1024 |
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#endif |
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/* Intel MP Floating Pointer Structure */ |
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struct mpf_intel { |
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char signature[4]; /* "_MP_" */ |
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unsigned int physptr; /* Configuration table address */ |
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unsigned char length; /* Our length (paragraphs) */ |
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unsigned char specification; /* Specification version */ |
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unsigned char checksum; /* Checksum (makes sum 0) */ |
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unsigned char feature1; /* Standard or configuration ? */ |
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unsigned char feature2; /* Bit7 set for IMCR|PIC */ |
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unsigned char feature3; /* Unused (0) */ |
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unsigned char feature4; /* Unused (0) */ |
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unsigned char feature5; /* Unused (0) */ |
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}; |
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#define MPC_SIGNATURE "PCMP" |
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struct mpc_table { |
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char signature[4]; |
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unsigned short length; /* Size of table */ |
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char spec; /* 0x01 */ |
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char checksum; |
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char oem[8]; |
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char productid[12]; |
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unsigned int oemptr; /* 0 if not present */ |
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unsigned short oemsize; /* 0 if not present */ |
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unsigned short oemcount; |
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unsigned int lapic; /* APIC address */ |
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unsigned int reserved; |
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}; |
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/* Followed by entries */ |
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#define MP_PROCESSOR 0 |
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#define MP_BUS 1 |
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#define MP_IOAPIC 2 |
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#define MP_INTSRC 3 |
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#define MP_LINTSRC 4 |
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/* Used by IBM NUMA-Q to describe node locality */ |
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#define MP_TRANSLATION 192 |
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#define CPU_ENABLED 1 /* Processor is available */ |
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#define CPU_BOOTPROCESSOR 2 /* Processor is the boot CPU */ |
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#define CPU_STEPPING_MASK 0x000F |
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#define CPU_MODEL_MASK 0x00F0 |
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#define CPU_FAMILY_MASK 0x0F00 |
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struct mpc_cpu { |
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unsigned char type; |
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unsigned char apicid; /* Local APIC number */ |
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unsigned char apicver; /* Its versions */ |
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unsigned char cpuflag; |
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unsigned int cpufeature; |
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unsigned int featureflag; /* CPUID feature value */ |
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unsigned int reserved[2]; |
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}; |
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struct mpc_bus { |
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unsigned char type; |
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unsigned char busid; |
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unsigned char bustype[6]; |
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}; |
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/* List of Bus Type string values, Intel MP Spec. */ |
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#define BUSTYPE_EISA "EISA" |
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#define BUSTYPE_ISA "ISA" |
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#define BUSTYPE_INTERN "INTERN" /* Internal BUS */ |
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#define BUSTYPE_MCA "MCA" /* Obsolete */ |
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#define BUSTYPE_VL "VL" /* Local bus */ |
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#define BUSTYPE_PCI "PCI" |
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#define BUSTYPE_PCMCIA "PCMCIA" |
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#define BUSTYPE_CBUS "CBUS" |
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#define BUSTYPE_CBUSII "CBUSII" |
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#define BUSTYPE_FUTURE "FUTURE" |
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#define BUSTYPE_MBI "MBI" |
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#define BUSTYPE_MBII "MBII" |
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#define BUSTYPE_MPI "MPI" |
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#define BUSTYPE_MPSA "MPSA" |
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#define BUSTYPE_NUBUS "NUBUS" |
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#define BUSTYPE_TC "TC" |
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#define BUSTYPE_VME "VME" |
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#define BUSTYPE_XPRESS "XPRESS" |
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#define MPC_APIC_USABLE 0x01 |
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struct mpc_ioapic { |
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unsigned char type; |
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unsigned char apicid; |
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unsigned char apicver; |
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unsigned char flags; |
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unsigned int apicaddr; |
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}; |
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struct mpc_intsrc { |
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unsigned char type; |
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unsigned char irqtype; |
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unsigned short irqflag; |
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unsigned char srcbus; |
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unsigned char srcbusirq; |
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unsigned char dstapic; |
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unsigned char dstirq; |
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}; |
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enum mp_irq_source_types { |
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mp_INT = 0, |
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mp_NMI = 1, |
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mp_SMI = 2, |
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mp_ExtINT = 3 |
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}; |
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#define MP_IRQPOL_DEFAULT 0x0 |
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#define MP_IRQPOL_ACTIVE_HIGH 0x1 |
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#define MP_IRQPOL_RESERVED 0x2 |
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#define MP_IRQPOL_ACTIVE_LOW 0x3 |
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#define MP_IRQPOL_MASK 0x3 |
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#define MP_IRQTRIG_DEFAULT 0x0 |
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#define MP_IRQTRIG_EDGE 0x4 |
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#define MP_IRQTRIG_RESERVED 0x8 |
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#define MP_IRQTRIG_LEVEL 0xc |
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#define MP_IRQTRIG_MASK 0xc |
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#define MP_APIC_ALL 0xFF |
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struct mpc_lintsrc { |
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unsigned char type; |
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unsigned char irqtype; |
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unsigned short irqflag; |
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unsigned char srcbusid; |
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unsigned char srcbusirq; |
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unsigned char destapic; |
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unsigned char destapiclint; |
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}; |
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#define MPC_OEM_SIGNATURE "_OEM" |
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struct mpc_oemtable { |
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char signature[4]; |
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unsigned short length; /* Size of table */ |
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char rev; /* 0x01 */ |
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char checksum; |
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char mpc[8]; |
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}; |
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/* |
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* Default configurations |
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* |
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* 1 2 CPU ISA 82489DX |
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* 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining |
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* 3 2 CPU EISA 82489DX |
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* 4 2 CPU MCA 82489DX |
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* 5 2 CPU ISA+PCI |
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* 6 2 CPU EISA+PCI |
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* 7 2 CPU MCA+PCI |
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*/ |
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enum mp_bustype { |
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MP_BUS_ISA = 1, |
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MP_BUS_EISA, |
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MP_BUS_PCI, |
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}; |
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#endif /* _ASM_X86_MPSPEC_DEF_H */
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