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444 lines
11 KiB
444 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_APICDEF_H |
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#define _ASM_X86_APICDEF_H |
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/* |
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* Constants for various Intel APICs. (local APIC, IOAPIC, etc.) |
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* |
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* Alan Cox <[email protected]>, 1995. |
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* Ingo Molnar <[email protected]>, 1999, 2000 |
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*/ |
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#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 |
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#define APIC_DEFAULT_PHYS_BASE 0xfee00000 |
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/* |
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* This is the IO-APIC register space as specified |
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* by Intel docs: |
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*/ |
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#define IO_APIC_SLOT_SIZE 1024 |
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#define APIC_ID 0x20 |
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#define APIC_LVR 0x30 |
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#define APIC_LVR_MASK 0xFF00FF |
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#define APIC_LVR_DIRECTED_EOI (1 << 24) |
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#define GET_APIC_VERSION(x) ((x) & 0xFFu) |
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#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) |
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#ifdef CONFIG_X86_32 |
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# define APIC_INTEGRATED(x) ((x) & 0xF0u) |
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#else |
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# define APIC_INTEGRATED(x) (1) |
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#endif |
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#define APIC_XAPIC(x) ((x) >= 0x14) |
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#define APIC_EXT_SPACE(x) ((x) & 0x80000000) |
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#define APIC_TASKPRI 0x80 |
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#define APIC_TPRI_MASK 0xFFu |
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#define APIC_ARBPRI 0x90 |
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#define APIC_ARBPRI_MASK 0xFFu |
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#define APIC_PROCPRI 0xA0 |
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#define APIC_EOI 0xB0 |
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#define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */ |
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#define APIC_RRR 0xC0 |
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#define APIC_LDR 0xD0 |
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#define APIC_LDR_MASK (0xFFu << 24) |
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#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) |
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#define SET_APIC_LOGICAL_ID(x) (((x) << 24)) |
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#define APIC_ALL_CPUS 0xFFu |
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#define APIC_DFR 0xE0 |
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#define APIC_DFR_CLUSTER 0x0FFFFFFFul |
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#define APIC_DFR_FLAT 0xFFFFFFFFul |
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#define APIC_SPIV 0xF0 |
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#define APIC_SPIV_DIRECTED_EOI (1 << 12) |
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#define APIC_SPIV_FOCUS_DISABLED (1 << 9) |
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#define APIC_SPIV_APIC_ENABLED (1 << 8) |
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#define APIC_ISR 0x100 |
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#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ |
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#define APIC_TMR 0x180 |
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#define APIC_IRR 0x200 |
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#define APIC_ESR 0x280 |
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#define APIC_ESR_SEND_CS 0x00001 |
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#define APIC_ESR_RECV_CS 0x00002 |
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#define APIC_ESR_SEND_ACC 0x00004 |
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#define APIC_ESR_RECV_ACC 0x00008 |
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#define APIC_ESR_SENDILL 0x00020 |
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#define APIC_ESR_RECVILL 0x00040 |
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#define APIC_ESR_ILLREGA 0x00080 |
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#define APIC_LVTCMCI 0x2f0 |
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#define APIC_ICR 0x300 |
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#define APIC_DEST_SELF 0x40000 |
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#define APIC_DEST_ALLINC 0x80000 |
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#define APIC_DEST_ALLBUT 0xC0000 |
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#define APIC_ICR_RR_MASK 0x30000 |
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#define APIC_ICR_RR_INVALID 0x00000 |
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#define APIC_ICR_RR_INPROG 0x10000 |
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#define APIC_ICR_RR_VALID 0x20000 |
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#define APIC_INT_LEVELTRIG 0x08000 |
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#define APIC_INT_ASSERT 0x04000 |
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#define APIC_ICR_BUSY 0x01000 |
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#define APIC_DEST_LOGICAL 0x00800 |
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#define APIC_DEST_PHYSICAL 0x00000 |
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#define APIC_DM_FIXED 0x00000 |
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#define APIC_DM_FIXED_MASK 0x00700 |
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#define APIC_DM_LOWEST 0x00100 |
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#define APIC_DM_SMI 0x00200 |
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#define APIC_DM_REMRD 0x00300 |
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#define APIC_DM_NMI 0x00400 |
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#define APIC_DM_INIT 0x00500 |
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#define APIC_DM_STARTUP 0x00600 |
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#define APIC_DM_EXTINT 0x00700 |
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#define APIC_VECTOR_MASK 0x000FF |
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#define APIC_ICR2 0x310 |
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#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) |
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#define SET_APIC_DEST_FIELD(x) ((x) << 24) |
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#define APIC_LVTT 0x320 |
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#define APIC_LVTTHMR 0x330 |
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#define APIC_LVTPC 0x340 |
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#define APIC_LVT0 0x350 |
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#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) |
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#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) |
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#define SET_APIC_TIMER_BASE(x) (((x) << 18)) |
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#define APIC_TIMER_BASE_CLKIN 0x0 |
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#define APIC_TIMER_BASE_TMBASE 0x1 |
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#define APIC_TIMER_BASE_DIV 0x2 |
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#define APIC_LVT_TIMER_ONESHOT (0 << 17) |
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#define APIC_LVT_TIMER_PERIODIC (1 << 17) |
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#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) |
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#define APIC_LVT_MASKED (1 << 16) |
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#define APIC_LVT_LEVEL_TRIGGER (1 << 15) |
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#define APIC_LVT_REMOTE_IRR (1 << 14) |
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#define APIC_INPUT_POLARITY (1 << 13) |
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#define APIC_SEND_PENDING (1 << 12) |
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#define APIC_MODE_MASK 0x700 |
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#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) |
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#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) |
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#define APIC_MODE_FIXED 0x0 |
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#define APIC_MODE_NMI 0x4 |
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#define APIC_MODE_EXTINT 0x7 |
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#define APIC_LVT1 0x360 |
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#define APIC_LVTERR 0x370 |
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#define APIC_TMICT 0x380 |
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#define APIC_TMCCT 0x390 |
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#define APIC_TDCR 0x3E0 |
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#define APIC_SELF_IPI 0x3F0 |
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#define APIC_TDR_DIV_TMBASE (1 << 2) |
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#define APIC_TDR_DIV_1 0xB |
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#define APIC_TDR_DIV_2 0x0 |
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#define APIC_TDR_DIV_4 0x1 |
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#define APIC_TDR_DIV_8 0x2 |
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#define APIC_TDR_DIV_16 0x3 |
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#define APIC_TDR_DIV_32 0x8 |
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#define APIC_TDR_DIV_64 0x9 |
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#define APIC_TDR_DIV_128 0xA |
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#define APIC_EFEAT 0x400 |
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#define APIC_ECTRL 0x410 |
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#define APIC_EILVTn(n) (0x500 + 0x10 * n) |
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#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ |
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#define APIC_EILVT_NR_AMD_10H 4 |
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#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H |
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#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) |
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#define APIC_EILVT_MSG_FIX 0x0 |
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#define APIC_EILVT_MSG_SMI 0x2 |
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#define APIC_EILVT_MSG_NMI 0x4 |
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#define APIC_EILVT_MSG_EXT 0x7 |
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#define APIC_EILVT_MASKED (1 << 16) |
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#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) |
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#define APIC_BASE_MSR 0x800 |
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#define XAPIC_ENABLE (1UL << 11) |
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#define X2APIC_ENABLE (1UL << 10) |
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#ifdef CONFIG_X86_32 |
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# define MAX_IO_APICS 64 |
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# define MAX_LOCAL_APIC 256 |
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#else |
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# define MAX_IO_APICS 128 |
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# define MAX_LOCAL_APIC 32768 |
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#endif |
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/* |
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* All x86-64 systems are xAPIC compatible. |
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* In the following, "apicid" is a physical APIC ID. |
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*/ |
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#define XAPIC_DEST_CPUS_SHIFT 4 |
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#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) |
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#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) |
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#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) |
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#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) |
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#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) |
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#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) |
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/* |
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* the local APIC register structure, memory mapped. Not terribly well |
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* tested, but we might eventually use this one in the future - the |
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* problem why we cannot use it right now is the P5 APIC, it has an |
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* errata which cannot take 8-bit reads and writes, only 32-bit ones ... |
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*/ |
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#define u32 unsigned int |
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struct local_apic { |
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/*000*/ struct { u32 __reserved[4]; } __reserved_01; |
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/*010*/ struct { u32 __reserved[4]; } __reserved_02; |
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/*020*/ struct { /* APIC ID Register */ |
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u32 __reserved_1 : 24, |
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phys_apic_id : 4, |
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__reserved_2 : 4; |
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u32 __reserved[3]; |
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} id; |
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/*030*/ const |
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struct { /* APIC Version Register */ |
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u32 version : 8, |
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__reserved_1 : 8, |
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max_lvt : 8, |
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__reserved_2 : 8; |
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u32 __reserved[3]; |
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} version; |
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/*040*/ struct { u32 __reserved[4]; } __reserved_03; |
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/*050*/ struct { u32 __reserved[4]; } __reserved_04; |
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/*060*/ struct { u32 __reserved[4]; } __reserved_05; |
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/*070*/ struct { u32 __reserved[4]; } __reserved_06; |
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/*080*/ struct { /* Task Priority Register */ |
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u32 priority : 8, |
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__reserved_1 : 24; |
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u32 __reserved_2[3]; |
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} tpr; |
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/*090*/ const |
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struct { /* Arbitration Priority Register */ |
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u32 priority : 8, |
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__reserved_1 : 24; |
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u32 __reserved_2[3]; |
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} apr; |
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/*0A0*/ const |
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struct { /* Processor Priority Register */ |
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u32 priority : 8, |
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__reserved_1 : 24; |
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u32 __reserved_2[3]; |
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} ppr; |
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/*0B0*/ struct { /* End Of Interrupt Register */ |
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u32 eoi; |
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u32 __reserved[3]; |
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} eoi; |
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/*0C0*/ struct { u32 __reserved[4]; } __reserved_07; |
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/*0D0*/ struct { /* Logical Destination Register */ |
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u32 __reserved_1 : 24, |
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logical_dest : 8; |
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u32 __reserved_2[3]; |
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} ldr; |
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/*0E0*/ struct { /* Destination Format Register */ |
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u32 __reserved_1 : 28, |
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model : 4; |
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u32 __reserved_2[3]; |
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} dfr; |
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/*0F0*/ struct { /* Spurious Interrupt Vector Register */ |
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u32 spurious_vector : 8, |
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apic_enabled : 1, |
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focus_cpu : 1, |
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__reserved_2 : 22; |
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u32 __reserved_3[3]; |
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} svr; |
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/*100*/ struct { /* In Service Register */ |
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/*170*/ u32 bitfield; |
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u32 __reserved[3]; |
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} isr [8]; |
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/*180*/ struct { /* Trigger Mode Register */ |
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/*1F0*/ u32 bitfield; |
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u32 __reserved[3]; |
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} tmr [8]; |
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/*200*/ struct { /* Interrupt Request Register */ |
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/*270*/ u32 bitfield; |
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u32 __reserved[3]; |
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} irr [8]; |
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/*280*/ union { /* Error Status Register */ |
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struct { |
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u32 send_cs_error : 1, |
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receive_cs_error : 1, |
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send_accept_error : 1, |
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receive_accept_error : 1, |
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__reserved_1 : 1, |
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send_illegal_vector : 1, |
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receive_illegal_vector : 1, |
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illegal_register_address : 1, |
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__reserved_2 : 24; |
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u32 __reserved_3[3]; |
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} error_bits; |
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struct { |
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u32 errors; |
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u32 __reserved_3[3]; |
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} all_errors; |
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} esr; |
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/*290*/ struct { u32 __reserved[4]; } __reserved_08; |
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/*2A0*/ struct { u32 __reserved[4]; } __reserved_09; |
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/*2B0*/ struct { u32 __reserved[4]; } __reserved_10; |
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/*2C0*/ struct { u32 __reserved[4]; } __reserved_11; |
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/*2D0*/ struct { u32 __reserved[4]; } __reserved_12; |
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/*2E0*/ struct { u32 __reserved[4]; } __reserved_13; |
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/*2F0*/ struct { u32 __reserved[4]; } __reserved_14; |
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/*300*/ struct { /* Interrupt Command Register 1 */ |
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u32 vector : 8, |
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delivery_mode : 3, |
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destination_mode : 1, |
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delivery_status : 1, |
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__reserved_1 : 1, |
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level : 1, |
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trigger : 1, |
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__reserved_2 : 2, |
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shorthand : 2, |
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__reserved_3 : 12; |
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u32 __reserved_4[3]; |
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} icr1; |
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/*310*/ struct { /* Interrupt Command Register 2 */ |
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union { |
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u32 __reserved_1 : 24, |
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phys_dest : 4, |
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__reserved_2 : 4; |
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u32 __reserved_3 : 24, |
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logical_dest : 8; |
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} dest; |
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u32 __reserved_4[3]; |
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} icr2; |
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/*320*/ struct { /* LVT - Timer */ |
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u32 vector : 8, |
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__reserved_1 : 4, |
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delivery_status : 1, |
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__reserved_2 : 3, |
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mask : 1, |
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timer_mode : 1, |
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__reserved_3 : 14; |
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u32 __reserved_4[3]; |
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} lvt_timer; |
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/*330*/ struct { /* LVT - Thermal Sensor */ |
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u32 vector : 8, |
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delivery_mode : 3, |
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__reserved_1 : 1, |
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delivery_status : 1, |
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__reserved_2 : 3, |
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mask : 1, |
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__reserved_3 : 15; |
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u32 __reserved_4[3]; |
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} lvt_thermal; |
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/*340*/ struct { /* LVT - Performance Counter */ |
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u32 vector : 8, |
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delivery_mode : 3, |
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__reserved_1 : 1, |
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delivery_status : 1, |
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__reserved_2 : 3, |
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mask : 1, |
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__reserved_3 : 15; |
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u32 __reserved_4[3]; |
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} lvt_pc; |
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/*350*/ struct { /* LVT - LINT0 */ |
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u32 vector : 8, |
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delivery_mode : 3, |
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__reserved_1 : 1, |
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delivery_status : 1, |
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polarity : 1, |
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remote_irr : 1, |
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trigger : 1, |
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mask : 1, |
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__reserved_2 : 15; |
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u32 __reserved_3[3]; |
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} lvt_lint0; |
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/*360*/ struct { /* LVT - LINT1 */ |
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u32 vector : 8, |
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delivery_mode : 3, |
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__reserved_1 : 1, |
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delivery_status : 1, |
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polarity : 1, |
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remote_irr : 1, |
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trigger : 1, |
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mask : 1, |
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__reserved_2 : 15; |
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u32 __reserved_3[3]; |
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} lvt_lint1; |
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/*370*/ struct { /* LVT - Error */ |
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u32 vector : 8, |
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__reserved_1 : 4, |
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delivery_status : 1, |
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__reserved_2 : 3, |
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mask : 1, |
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__reserved_3 : 15; |
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u32 __reserved_4[3]; |
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} lvt_error; |
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/*380*/ struct { /* Timer Initial Count Register */ |
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u32 initial_count; |
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u32 __reserved_2[3]; |
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} timer_icr; |
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/*390*/ const |
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struct { /* Timer Current Count Register */ |
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u32 curr_count; |
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u32 __reserved_2[3]; |
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} timer_ccr; |
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/*3A0*/ struct { u32 __reserved[4]; } __reserved_16; |
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/*3B0*/ struct { u32 __reserved[4]; } __reserved_17; |
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/*3C0*/ struct { u32 __reserved[4]; } __reserved_18; |
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/*3D0*/ struct { u32 __reserved[4]; } __reserved_19; |
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/*3E0*/ struct { /* Timer Divide Configuration Register */ |
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u32 divisor : 4, |
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__reserved_1 : 28; |
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u32 __reserved_2[3]; |
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} timer_dcr; |
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/*3F0*/ struct { u32 __reserved[4]; } __reserved_20; |
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} __attribute__ ((packed)); |
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#undef u32 |
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#ifdef CONFIG_X86_32 |
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#define BAD_APICID 0xFFu |
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#else |
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#define BAD_APICID 0xFFFFu |
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#endif |
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enum apic_delivery_modes { |
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APIC_DELIVERY_MODE_FIXED = 0, |
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APIC_DELIVERY_MODE_LOWESTPRIO = 1, |
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APIC_DELIVERY_MODE_SMI = 2, |
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APIC_DELIVERY_MODE_NMI = 4, |
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APIC_DELIVERY_MODE_INIT = 5, |
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APIC_DELIVERY_MODE_EXTINT = 7, |
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}; |
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#endif /* _ASM_X86_APICDEF_H */
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