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613 lines
14 KiB
613 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Zhaoxin PMU; like Intel Architectural PerfMon-v2 |
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*/ |
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|
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/stddef.h> |
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#include <linux/types.h> |
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#include <linux/init.h> |
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#include <linux/slab.h> |
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#include <linux/export.h> |
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#include <linux/nmi.h> |
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#include <asm/cpufeature.h> |
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#include <asm/hardirq.h> |
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#include <asm/apic.h> |
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#include "../perf_event.h" |
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/* |
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* Zhaoxin PerfMon, used on zxc and later. |
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*/ |
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static u64 zx_pmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = { |
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0082, |
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0515, |
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[PERF_COUNT_HW_CACHE_MISSES] = 0x051a, |
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[PERF_COUNT_HW_BUS_CYCLES] = 0x0083, |
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}; |
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static struct event_constraint zxc_event_constraints[] __read_mostly = { |
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FIXED_EVENT_CONSTRAINT(0x0082, 1), /* unhalted core clock cycles */ |
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EVENT_CONSTRAINT_END |
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}; |
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static struct event_constraint zxd_event_constraints[] __read_mostly = { |
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* retired instructions */ |
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FIXED_EVENT_CONSTRAINT(0x0082, 1), /* unhalted core clock cycles */ |
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FIXED_EVENT_CONSTRAINT(0x0083, 2), /* unhalted bus clock cycles */ |
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EVENT_CONSTRAINT_END |
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}; |
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static __initconst const u64 zxd_hw_cache_event_ids |
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[PERF_COUNT_HW_CACHE_MAX] |
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[PERF_COUNT_HW_CACHE_OP_MAX] |
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
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[C(L1D)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0042, |
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[C(RESULT_MISS)] = 0x0538, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = 0x0043, |
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[C(RESULT_MISS)] = 0x0562, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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[C(L1I)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0300, |
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[C(RESULT_MISS)] = 0x0301, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = 0x030a, |
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[C(RESULT_MISS)] = 0x030b, |
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}, |
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}, |
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[C(LL)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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[C(DTLB)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0042, |
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[C(RESULT_MISS)] = 0x052c, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = 0x0043, |
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[C(RESULT_MISS)] = 0x0530, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = 0x0564, |
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[C(RESULT_MISS)] = 0x0565, |
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}, |
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}, |
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[C(ITLB)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x00c0, |
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[C(RESULT_MISS)] = 0x0534, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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[C(BPU)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0700, |
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[C(RESULT_MISS)] = 0x0709, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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[C(NODE)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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}; |
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static __initconst const u64 zxe_hw_cache_event_ids |
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[PERF_COUNT_HW_CACHE_MAX] |
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[PERF_COUNT_HW_CACHE_OP_MAX] |
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
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[C(L1D)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0568, |
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[C(RESULT_MISS)] = 0x054b, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = 0x0669, |
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[C(RESULT_MISS)] = 0x0562, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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[C(L1I)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0300, |
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[C(RESULT_MISS)] = 0x0301, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = 0x030a, |
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[C(RESULT_MISS)] = 0x030b, |
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}, |
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}, |
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[C(LL)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0, |
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[C(RESULT_MISS)] = 0x0, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = 0x0, |
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[C(RESULT_MISS)] = 0x0, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = 0x0, |
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[C(RESULT_MISS)] = 0x0, |
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}, |
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}, |
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[C(DTLB)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0568, |
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[C(RESULT_MISS)] = 0x052c, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = 0x0669, |
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[C(RESULT_MISS)] = 0x0530, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = 0x0564, |
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[C(RESULT_MISS)] = 0x0565, |
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}, |
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}, |
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[C(ITLB)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x00c0, |
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[C(RESULT_MISS)] = 0x0534, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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[C(BPU)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = 0x0028, |
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[C(RESULT_MISS)] = 0x0029, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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[C(NODE)] = { |
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[C(OP_READ)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_WRITE)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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[C(OP_PREFETCH)] = { |
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[C(RESULT_ACCESS)] = -1, |
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[C(RESULT_MISS)] = -1, |
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}, |
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}, |
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}; |
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static void zhaoxin_pmu_disable_all(void) |
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{ |
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
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} |
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static void zhaoxin_pmu_enable_all(int added) |
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{ |
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
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} |
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static inline u64 zhaoxin_pmu_get_status(void) |
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{ |
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u64 status; |
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rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
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return status; |
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} |
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static inline void zhaoxin_pmu_ack_status(u64 ack) |
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{ |
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wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); |
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} |
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static inline void zxc_pmu_ack_status(u64 ack) |
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{ |
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/* |
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* ZXC needs global control enabled in order to clear status bits. |
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*/ |
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zhaoxin_pmu_enable_all(0); |
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zhaoxin_pmu_ack_status(ack); |
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zhaoxin_pmu_disable_all(); |
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} |
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static void zhaoxin_pmu_disable_fixed(struct hw_perf_event *hwc) |
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{ |
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int idx = hwc->idx - INTEL_PMC_IDX_FIXED; |
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u64 ctrl_val, mask; |
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mask = 0xfULL << (idx * 4); |
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rdmsrl(hwc->config_base, ctrl_val); |
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ctrl_val &= ~mask; |
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wrmsrl(hwc->config_base, ctrl_val); |
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} |
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static void zhaoxin_pmu_disable_event(struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
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zhaoxin_pmu_disable_fixed(hwc); |
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return; |
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} |
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x86_pmu_disable_event(event); |
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} |
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static void zhaoxin_pmu_enable_fixed(struct hw_perf_event *hwc) |
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{ |
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int idx = hwc->idx - INTEL_PMC_IDX_FIXED; |
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u64 ctrl_val, bits, mask; |
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/* |
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* Enable IRQ generation (0x8), |
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* and enable ring-3 counting (0x2) and ring-0 counting (0x1) |
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* if requested: |
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*/ |
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bits = 0x8ULL; |
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if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) |
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bits |= 0x2; |
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if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
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bits |= 0x1; |
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bits <<= (idx * 4); |
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mask = 0xfULL << (idx * 4); |
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rdmsrl(hwc->config_base, ctrl_val); |
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ctrl_val &= ~mask; |
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ctrl_val |= bits; |
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wrmsrl(hwc->config_base, ctrl_val); |
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} |
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static void zhaoxin_pmu_enable_event(struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
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zhaoxin_pmu_enable_fixed(hwc); |
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return; |
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} |
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__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
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} |
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/* |
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* This handler is triggered by the local APIC, so the APIC IRQ handling |
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* rules apply: |
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*/ |
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static int zhaoxin_pmu_handle_irq(struct pt_regs *regs) |
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{ |
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struct perf_sample_data data; |
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struct cpu_hw_events *cpuc; |
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int handled = 0; |
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u64 status; |
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int bit; |
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cpuc = this_cpu_ptr(&cpu_hw_events); |
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apic_write(APIC_LVTPC, APIC_DM_NMI); |
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zhaoxin_pmu_disable_all(); |
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status = zhaoxin_pmu_get_status(); |
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if (!status) |
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goto done; |
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again: |
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if (x86_pmu.enabled_ack) |
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zxc_pmu_ack_status(status); |
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else |
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zhaoxin_pmu_ack_status(status); |
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inc_irq_stat(apic_perf_irqs); |
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/* |
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* CondChgd bit 63 doesn't mean any overflow status. Ignore |
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* and clear the bit. |
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*/ |
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if (__test_and_clear_bit(63, (unsigned long *)&status)) { |
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if (!status) |
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goto done; |
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} |
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for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
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struct perf_event *event = cpuc->events[bit]; |
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handled++; |
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if (!test_bit(bit, cpuc->active_mask)) |
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continue; |
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x86_perf_event_update(event); |
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perf_sample_data_init(&data, 0, event->hw.last_period); |
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if (!x86_perf_event_set_period(event)) |
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continue; |
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if (perf_event_overflow(event, &data, regs)) |
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x86_pmu_stop(event, 0); |
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} |
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/* |
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* Repeat if there is more work to be done: |
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*/ |
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status = zhaoxin_pmu_get_status(); |
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if (status) |
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goto again; |
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done: |
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zhaoxin_pmu_enable_all(0); |
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return handled; |
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} |
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static u64 zhaoxin_pmu_event_map(int hw_event) |
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{ |
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return zx_pmon_event_map[hw_event]; |
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} |
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static struct event_constraint * |
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zhaoxin_get_event_constraints(struct cpu_hw_events *cpuc, int idx, |
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struct perf_event *event) |
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{ |
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struct event_constraint *c; |
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if (x86_pmu.event_constraints) { |
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for_each_event_constraint(c, x86_pmu.event_constraints) { |
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if ((event->hw.config & c->cmask) == c->code) |
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return c; |
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} |
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} |
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return &unconstrained; |
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} |
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PMU_FORMAT_ATTR(event, "config:0-7"); |
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PMU_FORMAT_ATTR(umask, "config:8-15"); |
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PMU_FORMAT_ATTR(edge, "config:18"); |
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PMU_FORMAT_ATTR(inv, "config:23"); |
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PMU_FORMAT_ATTR(cmask, "config:24-31"); |
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static struct attribute *zx_arch_formats_attr[] = { |
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&format_attr_event.attr, |
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&format_attr_umask.attr, |
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&format_attr_edge.attr, |
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&format_attr_inv.attr, |
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&format_attr_cmask.attr, |
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NULL, |
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}; |
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static ssize_t zhaoxin_event_sysfs_show(char *page, u64 config) |
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{ |
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u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); |
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return x86_event_sysfs_show(page, config, event); |
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} |
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static const struct x86_pmu zhaoxin_pmu __initconst = { |
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.name = "zhaoxin", |
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.handle_irq = zhaoxin_pmu_handle_irq, |
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.disable_all = zhaoxin_pmu_disable_all, |
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.enable_all = zhaoxin_pmu_enable_all, |
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.enable = zhaoxin_pmu_enable_event, |
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.disable = zhaoxin_pmu_disable_event, |
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.hw_config = x86_pmu_hw_config, |
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.schedule_events = x86_schedule_events, |
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.eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
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.perfctr = MSR_ARCH_PERFMON_PERFCTR0, |
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.event_map = zhaoxin_pmu_event_map, |
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.max_events = ARRAY_SIZE(zx_pmon_event_map), |
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.apic = 1, |
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/* |
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* For zxd/zxe, read/write operation for PMCx MSR is 48 bits. |
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*/ |
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.max_period = (1ULL << 47) - 1, |
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.get_event_constraints = zhaoxin_get_event_constraints, |
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.format_attrs = zx_arch_formats_attr, |
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.events_sysfs_show = zhaoxin_event_sysfs_show, |
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}; |
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static const struct { int id; char *name; } zx_arch_events_map[] __initconst = { |
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{ PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, |
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{ PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, |
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{ PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, |
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{ PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, |
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{ PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, |
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{ PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, |
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{ PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, |
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}; |
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static __init void zhaoxin_arch_events_quirk(void) |
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{ |
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int bit; |
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/* disable event that reported as not presend by cpuid */ |
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for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(zx_arch_events_map)) { |
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zx_pmon_event_map[zx_arch_events_map[bit].id] = 0; |
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pr_warn("CPUID marked event: \'%s\' unavailable\n", |
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zx_arch_events_map[bit].name); |
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} |
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} |
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__init int zhaoxin_pmu_init(void) |
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{ |
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union cpuid10_edx edx; |
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union cpuid10_eax eax; |
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union cpuid10_ebx ebx; |
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struct event_constraint *c; |
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unsigned int unused; |
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int version; |
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pr_info("Welcome to zhaoxin pmu!\n"); |
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/* |
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* Check whether the Architectural PerfMon supports |
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* hw_event or not. |
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*/ |
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cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); |
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if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT - 1) |
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return -ENODEV; |
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version = eax.split.version_id; |
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if (version != 2) |
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return -ENODEV; |
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x86_pmu = zhaoxin_pmu; |
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pr_info("Version check pass!\n"); |
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x86_pmu.version = version; |
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x86_pmu.num_counters = eax.split.num_counters; |
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x86_pmu.cntval_bits = eax.split.bit_width; |
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x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; |
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x86_pmu.events_maskl = ebx.full; |
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x86_pmu.events_mask_len = eax.split.mask_length; |
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x86_pmu.num_counters_fixed = edx.split.num_counters_fixed; |
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x86_add_quirk(zhaoxin_arch_events_quirk); |
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switch (boot_cpu_data.x86) { |
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case 0x06: |
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if (boot_cpu_data.x86_model == 0x0f || boot_cpu_data.x86_model == 0x19) { |
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x86_pmu.max_period = x86_pmu.cntval_mask >> 1; |
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/* Clearing status works only if the global control is enable on zxc. */ |
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x86_pmu.enabled_ack = 1; |
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x86_pmu.event_constraints = zxc_event_constraints; |
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zx_pmon_event_map[PERF_COUNT_HW_INSTRUCTIONS] = 0; |
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zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0; |
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zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0; |
|
zx_pmon_event_map[PERF_COUNT_HW_BUS_CYCLES] = 0; |
|
|
|
pr_cont("ZXC events, "); |
|
break; |
|
} |
|
return -ENODEV; |
|
|
|
case 0x07: |
|
zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
|
X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); |
|
|
|
zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
|
X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); |
|
|
|
switch (boot_cpu_data.x86_model) { |
|
case 0x1b: |
|
memcpy(hw_cache_event_ids, zxd_hw_cache_event_ids, |
|
sizeof(hw_cache_event_ids)); |
|
|
|
x86_pmu.event_constraints = zxd_event_constraints; |
|
|
|
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0700; |
|
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0709; |
|
|
|
pr_cont("ZXD events, "); |
|
break; |
|
case 0x3b: |
|
memcpy(hw_cache_event_ids, zxe_hw_cache_event_ids, |
|
sizeof(hw_cache_event_ids)); |
|
|
|
x86_pmu.event_constraints = zxd_event_constraints; |
|
|
|
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028; |
|
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029; |
|
|
|
pr_cont("ZXE events, "); |
|
break; |
|
default: |
|
return -ENODEV; |
|
} |
|
break; |
|
|
|
default: |
|
return -ENODEV; |
|
} |
|
|
|
x86_pmu.intel_ctrl = (1 << (x86_pmu.num_counters)) - 1; |
|
x86_pmu.intel_ctrl |= ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; |
|
|
|
if (x86_pmu.event_constraints) { |
|
for_each_event_constraint(c, x86_pmu.event_constraints) { |
|
c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
|
c->weight += x86_pmu.num_counters; |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
|