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253 lines
5.9 KiB
253 lines
5.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* clear_page.S: UltraSparc optimized copy page. |
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* |
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* Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller (davem@redhat.com) |
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* Copyright (C) 1997 Jakub Jelinek (jakub@redhat.com) |
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*/ |
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#include <asm/visasm.h> |
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#include <asm/thread_info.h> |
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#include <asm/page.h> |
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#include <linux/pgtable.h> |
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#include <asm/spitfire.h> |
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#include <asm/head.h> |
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#include <asm/export.h> |
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/* What we used to do was lock a TLB entry into a specific |
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* TLB slot, clear the page with interrupts disabled, then |
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* restore the original TLB entry. This was great for |
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* disturbing the TLB as little as possible, but it meant |
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* we had to keep interrupts disabled for a long time. |
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* |
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* Now, we simply use the normal TLB loading mechanism, |
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* and this makes the cpu choose a slot all by itself. |
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* Then we do a normal TLB flush on exit. We need only |
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* disable preemption during the clear. |
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*/ |
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#define DCACHE_SIZE (PAGE_SIZE * 2) |
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#if (PAGE_SHIFT == 13) |
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#define PAGE_SIZE_REM 0x80 |
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#elif (PAGE_SHIFT == 16) |
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#define PAGE_SIZE_REM 0x100 |
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#else |
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#error Wrong PAGE_SHIFT specified |
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#endif |
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#define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7) \ |
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fsrc2 %reg0, %f48; fsrc2 %reg1, %f50; \ |
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fsrc2 %reg2, %f52; fsrc2 %reg3, %f54; \ |
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fsrc2 %reg4, %f56; fsrc2 %reg5, %f58; \ |
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fsrc2 %reg6, %f60; fsrc2 %reg7, %f62; |
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.text |
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.align 32 |
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.globl copy_user_page |
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.type copy_user_page,#function |
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EXPORT_SYMBOL(copy_user_page) |
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copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */ |
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lduw [%g6 + TI_PRE_COUNT], %o4 |
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sethi %hi(PAGE_OFFSET), %g2 |
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sethi %hi(PAGE_SIZE), %o3 |
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ldx [%g2 + %lo(PAGE_OFFSET)], %g2 |
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sethi %hi(PAGE_KERNEL_LOCKED), %g3 |
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ldx [%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3 |
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sub %o0, %g2, %g1 ! dest paddr |
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sub %o1, %g2, %g2 ! src paddr |
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and %o2, %o3, %o0 ! vaddr D-cache alias bit |
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or %g1, %g3, %g1 ! dest TTE data |
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or %g2, %g3, %g2 ! src TTE data |
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sethi %hi(TLBTEMP_BASE), %o3 |
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sethi %hi(DCACHE_SIZE), %o1 |
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add %o0, %o3, %o0 ! dest TTE vaddr |
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add %o4, 1, %o2 |
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add %o0, %o1, %o1 ! src TTE vaddr |
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/* Disable preemption. */ |
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mov TLB_TAG_ACCESS, %g3 |
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stw %o2, [%g6 + TI_PRE_COUNT] |
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/* Load TLB entries. */ |
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rdpr %pstate, %o2 |
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wrpr %o2, PSTATE_IE, %pstate |
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stxa %o0, [%g3] ASI_DMMU |
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stxa %g1, [%g0] ASI_DTLB_DATA_IN |
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membar #Sync |
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stxa %o1, [%g3] ASI_DMMU |
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stxa %g2, [%g0] ASI_DTLB_DATA_IN |
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membar #Sync |
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wrpr %o2, 0x0, %pstate |
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cheetah_copy_page_insn: |
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ba,pt %xcc, 9f |
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nop |
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1: |
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VISEntryHalf |
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membar #StoreLoad | #StoreStore | #LoadStore |
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sethi %hi((PAGE_SIZE/64)-2), %o2 |
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mov %o0, %g1 |
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prefetch [%o1 + 0x000], #one_read |
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or %o2, %lo((PAGE_SIZE/64)-2), %o2 |
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prefetch [%o1 + 0x040], #one_read |
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prefetch [%o1 + 0x080], #one_read |
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prefetch [%o1 + 0x0c0], #one_read |
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ldd [%o1 + 0x000], %f0 |
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prefetch [%o1 + 0x100], #one_read |
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ldd [%o1 + 0x008], %f2 |
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prefetch [%o1 + 0x140], #one_read |
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ldd [%o1 + 0x010], %f4 |
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prefetch [%o1 + 0x180], #one_read |
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fsrc2 %f0, %f16 |
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ldd [%o1 + 0x018], %f6 |
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fsrc2 %f2, %f18 |
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ldd [%o1 + 0x020], %f8 |
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fsrc2 %f4, %f20 |
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ldd [%o1 + 0x028], %f10 |
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fsrc2 %f6, %f22 |
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ldd [%o1 + 0x030], %f12 |
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fsrc2 %f8, %f24 |
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ldd [%o1 + 0x038], %f14 |
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fsrc2 %f10, %f26 |
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ldd [%o1 + 0x040], %f0 |
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1: ldd [%o1 + 0x048], %f2 |
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fsrc2 %f12, %f28 |
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ldd [%o1 + 0x050], %f4 |
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fsrc2 %f14, %f30 |
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stda %f16, [%o0] ASI_BLK_P |
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ldd [%o1 + 0x058], %f6 |
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fsrc2 %f0, %f16 |
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ldd [%o1 + 0x060], %f8 |
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fsrc2 %f2, %f18 |
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ldd [%o1 + 0x068], %f10 |
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fsrc2 %f4, %f20 |
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ldd [%o1 + 0x070], %f12 |
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fsrc2 %f6, %f22 |
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ldd [%o1 + 0x078], %f14 |
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fsrc2 %f8, %f24 |
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ldd [%o1 + 0x080], %f0 |
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prefetch [%o1 + 0x180], #one_read |
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fsrc2 %f10, %f26 |
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subcc %o2, 1, %o2 |
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add %o0, 0x40, %o0 |
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bne,pt %xcc, 1b |
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add %o1, 0x40, %o1 |
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ldd [%o1 + 0x048], %f2 |
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fsrc2 %f12, %f28 |
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ldd [%o1 + 0x050], %f4 |
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fsrc2 %f14, %f30 |
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stda %f16, [%o0] ASI_BLK_P |
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ldd [%o1 + 0x058], %f6 |
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fsrc2 %f0, %f16 |
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ldd [%o1 + 0x060], %f8 |
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fsrc2 %f2, %f18 |
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ldd [%o1 + 0x068], %f10 |
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fsrc2 %f4, %f20 |
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ldd [%o1 + 0x070], %f12 |
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fsrc2 %f6, %f22 |
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add %o0, 0x40, %o0 |
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ldd [%o1 + 0x078], %f14 |
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fsrc2 %f8, %f24 |
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fsrc2 %f10, %f26 |
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fsrc2 %f12, %f28 |
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fsrc2 %f14, %f30 |
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stda %f16, [%o0] ASI_BLK_P |
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membar #Sync |
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VISExitHalf |
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ba,pt %xcc, 5f |
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nop |
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9: |
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VISEntry |
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ldub [%g6 + TI_FAULT_CODE], %g3 |
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mov %o0, %g1 |
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cmp %g3, 0 |
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rd %asi, %g3 |
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be,a,pt %icc, 1f |
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wr %g0, ASI_BLK_P, %asi |
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wr %g0, ASI_BLK_COMMIT_P, %asi |
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1: ldda [%o1] ASI_BLK_P, %f0 |
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add %o1, 0x40, %o1 |
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ldda [%o1] ASI_BLK_P, %f16 |
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add %o1, 0x40, %o1 |
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sethi %hi(PAGE_SIZE), %o2 |
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1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14) |
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ldda [%o1] ASI_BLK_P, %f32 |
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stda %f48, [%o0] %asi |
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add %o1, 0x40, %o1 |
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sub %o2, 0x40, %o2 |
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add %o0, 0x40, %o0 |
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TOUCH(f16, f18, f20, f22, f24, f26, f28, f30) |
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ldda [%o1] ASI_BLK_P, %f0 |
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stda %f48, [%o0] %asi |
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add %o1, 0x40, %o1 |
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sub %o2, 0x40, %o2 |
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add %o0, 0x40, %o0 |
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TOUCH(f32, f34, f36, f38, f40, f42, f44, f46) |
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ldda [%o1] ASI_BLK_P, %f16 |
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stda %f48, [%o0] %asi |
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sub %o2, 0x40, %o2 |
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add %o1, 0x40, %o1 |
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cmp %o2, PAGE_SIZE_REM |
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bne,pt %xcc, 1b |
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add %o0, 0x40, %o0 |
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#if (PAGE_SHIFT == 16) |
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TOUCH(f0, f2, f4, f6, f8, f10, f12, f14) |
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ldda [%o1] ASI_BLK_P, %f32 |
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stda %f48, [%o0] %asi |
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add %o1, 0x40, %o1 |
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sub %o2, 0x40, %o2 |
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add %o0, 0x40, %o0 |
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TOUCH(f16, f18, f20, f22, f24, f26, f28, f30) |
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ldda [%o1] ASI_BLK_P, %f0 |
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stda %f48, [%o0] %asi |
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add %o1, 0x40, %o1 |
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sub %o2, 0x40, %o2 |
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add %o0, 0x40, %o0 |
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membar #Sync |
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stda %f32, [%o0] %asi |
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add %o0, 0x40, %o0 |
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stda %f0, [%o0] %asi |
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#else |
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membar #Sync |
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stda %f0, [%o0] %asi |
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add %o0, 0x40, %o0 |
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stda %f16, [%o0] %asi |
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#endif |
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membar #Sync |
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wr %g3, 0x0, %asi |
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VISExit |
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5: |
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stxa %g0, [%g1] ASI_DMMU_DEMAP |
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membar #Sync |
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sethi %hi(DCACHE_SIZE), %g2 |
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stxa %g0, [%g1 + %g2] ASI_DMMU_DEMAP |
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membar #Sync |
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retl |
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stw %o4, [%g6 + TI_PRE_COUNT] |
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.size copy_user_page, .-copy_user_page |
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.globl cheetah_patch_copy_page |
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cheetah_patch_copy_page: |
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sethi %hi(0x01000000), %o1 ! NOP |
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sethi %hi(cheetah_copy_page_insn), %o0 |
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or %o0, %lo(cheetah_copy_page_insn), %o0 |
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stw %o1, [%o0] |
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membar #StoreStore |
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flush %o0 |
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retl |
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nop
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