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899 lines
20 KiB
899 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* visemul.c: Emulation of VIS instructions. |
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* |
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* Copyright (C) 2006 David S. Miller ([email protected]) |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/thread_info.h> |
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#include <linux/perf_event.h> |
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#include <asm/ptrace.h> |
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#include <asm/pstate.h> |
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#include <asm/fpumacro.h> |
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#include <linux/uaccess.h> |
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#include <asm/cacheflush.h> |
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/* OPF field of various VIS instructions. */ |
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/* 000111011 - four 16-bit packs */ |
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#define FPACK16_OPF 0x03b |
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/* 000111010 - two 32-bit packs */ |
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#define FPACK32_OPF 0x03a |
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/* 000111101 - four 16-bit packs */ |
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#define FPACKFIX_OPF 0x03d |
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/* 001001101 - four 16-bit expands */ |
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#define FEXPAND_OPF 0x04d |
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/* 001001011 - two 32-bit merges */ |
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#define FPMERGE_OPF 0x04b |
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/* 000110001 - 8-by-16-bit partitioned product */ |
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#define FMUL8x16_OPF 0x031 |
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/* 000110011 - 8-by-16-bit upper alpha partitioned product */ |
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#define FMUL8x16AU_OPF 0x033 |
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/* 000110101 - 8-by-16-bit lower alpha partitioned product */ |
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#define FMUL8x16AL_OPF 0x035 |
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/* 000110110 - upper 8-by-16-bit partitioned product */ |
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#define FMUL8SUx16_OPF 0x036 |
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/* 000110111 - lower 8-by-16-bit partitioned product */ |
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#define FMUL8ULx16_OPF 0x037 |
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/* 000111000 - upper 8-by-16-bit partitioned product */ |
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#define FMULD8SUx16_OPF 0x038 |
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/* 000111001 - lower unsigned 8-by-16-bit partitioned product */ |
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#define FMULD8ULx16_OPF 0x039 |
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/* 000101000 - four 16-bit compare; set rd if src1 > src2 */ |
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#define FCMPGT16_OPF 0x028 |
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/* 000101100 - two 32-bit compare; set rd if src1 > src2 */ |
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#define FCMPGT32_OPF 0x02c |
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/* 000100000 - four 16-bit compare; set rd if src1 <= src2 */ |
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#define FCMPLE16_OPF 0x020 |
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/* 000100100 - two 32-bit compare; set rd if src1 <= src2 */ |
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#define FCMPLE32_OPF 0x024 |
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/* 000100010 - four 16-bit compare; set rd if src1 != src2 */ |
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#define FCMPNE16_OPF 0x022 |
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/* 000100110 - two 32-bit compare; set rd if src1 != src2 */ |
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#define FCMPNE32_OPF 0x026 |
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/* 000101010 - four 16-bit compare; set rd if src1 == src2 */ |
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#define FCMPEQ16_OPF 0x02a |
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/* 000101110 - two 32-bit compare; set rd if src1 == src2 */ |
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#define FCMPEQ32_OPF 0x02e |
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/* 000000000 - Eight 8-bit edge boundary processing */ |
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#define EDGE8_OPF 0x000 |
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/* 000000001 - Eight 8-bit edge boundary processing, no CC */ |
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#define EDGE8N_OPF 0x001 |
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/* 000000010 - Eight 8-bit edge boundary processing, little-endian */ |
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#define EDGE8L_OPF 0x002 |
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/* 000000011 - Eight 8-bit edge boundary processing, little-endian, no CC */ |
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#define EDGE8LN_OPF 0x003 |
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/* 000000100 - Four 16-bit edge boundary processing */ |
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#define EDGE16_OPF 0x004 |
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/* 000000101 - Four 16-bit edge boundary processing, no CC */ |
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#define EDGE16N_OPF 0x005 |
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/* 000000110 - Four 16-bit edge boundary processing, little-endian */ |
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#define EDGE16L_OPF 0x006 |
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/* 000000111 - Four 16-bit edge boundary processing, little-endian, no CC */ |
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#define EDGE16LN_OPF 0x007 |
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/* 000001000 - Two 32-bit edge boundary processing */ |
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#define EDGE32_OPF 0x008 |
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/* 000001001 - Two 32-bit edge boundary processing, no CC */ |
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#define EDGE32N_OPF 0x009 |
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/* 000001010 - Two 32-bit edge boundary processing, little-endian */ |
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#define EDGE32L_OPF 0x00a |
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/* 000001011 - Two 32-bit edge boundary processing, little-endian, no CC */ |
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#define EDGE32LN_OPF 0x00b |
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/* 000111110 - distance between 8 8-bit components */ |
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#define PDIST_OPF 0x03e |
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/* 000010000 - convert 8-bit 3-D address to blocked byte address */ |
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#define ARRAY8_OPF 0x010 |
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/* 000010010 - convert 16-bit 3-D address to blocked byte address */ |
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#define ARRAY16_OPF 0x012 |
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/* 000010100 - convert 32-bit 3-D address to blocked byte address */ |
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#define ARRAY32_OPF 0x014 |
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/* 000011001 - Set the GSR.MASK field in preparation for a BSHUFFLE */ |
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#define BMASK_OPF 0x019 |
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/* 001001100 - Permute bytes as specified by GSR.MASK */ |
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#define BSHUFFLE_OPF 0x04c |
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#define VIS_OPF_SHIFT 5 |
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#define VIS_OPF_MASK (0x1ff << VIS_OPF_SHIFT) |
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#define RS1(INSN) (((INSN) >> 14) & 0x1f) |
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#define RS2(INSN) (((INSN) >> 0) & 0x1f) |
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#define RD(INSN) (((INSN) >> 25) & 0x1f) |
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static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, |
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unsigned int rd, int from_kernel) |
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{ |
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if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { |
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if (from_kernel != 0) |
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__asm__ __volatile__("flushw"); |
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else |
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flushw_user(); |
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} |
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} |
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static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs) |
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{ |
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unsigned long value, fp; |
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if (reg < 16) |
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return (!reg ? 0 : regs->u_regs[reg]); |
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fp = regs->u_regs[UREG_FP]; |
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if (regs->tstate & TSTATE_PRIV) { |
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struct reg_window *win; |
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win = (struct reg_window *)(fp + STACK_BIAS); |
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value = win->locals[reg - 16]; |
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} else if (!test_thread_64bit_stack(fp)) { |
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struct reg_window32 __user *win32; |
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win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp)); |
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get_user(value, &win32->locals[reg - 16]); |
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} else { |
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struct reg_window __user *win; |
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win = (struct reg_window __user *)(fp + STACK_BIAS); |
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get_user(value, &win->locals[reg - 16]); |
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} |
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return value; |
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} |
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static inline unsigned long __user *__fetch_reg_addr_user(unsigned int reg, |
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struct pt_regs *regs) |
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{ |
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unsigned long fp = regs->u_regs[UREG_FP]; |
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BUG_ON(reg < 16); |
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BUG_ON(regs->tstate & TSTATE_PRIV); |
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if (!test_thread_64bit_stack(fp)) { |
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struct reg_window32 __user *win32; |
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win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp)); |
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return (unsigned long __user *)&win32->locals[reg - 16]; |
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} else { |
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struct reg_window __user *win; |
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win = (struct reg_window __user *)(fp + STACK_BIAS); |
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return &win->locals[reg - 16]; |
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} |
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} |
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static inline unsigned long *__fetch_reg_addr_kern(unsigned int reg, |
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struct pt_regs *regs) |
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{ |
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BUG_ON(reg >= 16); |
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BUG_ON(regs->tstate & TSTATE_PRIV); |
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return ®s->u_regs[reg]; |
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} |
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static void store_reg(struct pt_regs *regs, unsigned long val, unsigned long rd) |
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{ |
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if (rd < 16) { |
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unsigned long *rd_kern = __fetch_reg_addr_kern(rd, regs); |
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*rd_kern = val; |
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} else { |
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unsigned long __user *rd_user = __fetch_reg_addr_user(rd, regs); |
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if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) |
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__put_user((u32)val, (u32 __user *)rd_user); |
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else |
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__put_user(val, rd_user); |
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} |
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} |
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static inline unsigned long fpd_regval(struct fpustate *f, |
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unsigned int insn_regnum) |
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{ |
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insn_regnum = (((insn_regnum & 1) << 5) | |
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(insn_regnum & 0x1e)); |
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return *(unsigned long *) &f->regs[insn_regnum]; |
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} |
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static inline unsigned long *fpd_regaddr(struct fpustate *f, |
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unsigned int insn_regnum) |
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{ |
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insn_regnum = (((insn_regnum & 1) << 5) | |
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(insn_regnum & 0x1e)); |
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return (unsigned long *) &f->regs[insn_regnum]; |
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} |
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static inline unsigned int fps_regval(struct fpustate *f, |
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unsigned int insn_regnum) |
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{ |
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return f->regs[insn_regnum]; |
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} |
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static inline unsigned int *fps_regaddr(struct fpustate *f, |
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unsigned int insn_regnum) |
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{ |
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return &f->regs[insn_regnum]; |
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} |
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struct edge_tab { |
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u16 left, right; |
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}; |
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static struct edge_tab edge8_tab[8] = { |
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{ 0xff, 0x80 }, |
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{ 0x7f, 0xc0 }, |
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{ 0x3f, 0xe0 }, |
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{ 0x1f, 0xf0 }, |
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{ 0x0f, 0xf8 }, |
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{ 0x07, 0xfc }, |
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{ 0x03, 0xfe }, |
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{ 0x01, 0xff }, |
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}; |
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static struct edge_tab edge8_tab_l[8] = { |
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{ 0xff, 0x01 }, |
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{ 0xfe, 0x03 }, |
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{ 0xfc, 0x07 }, |
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{ 0xf8, 0x0f }, |
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{ 0xf0, 0x1f }, |
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{ 0xe0, 0x3f }, |
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{ 0xc0, 0x7f }, |
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{ 0x80, 0xff }, |
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}; |
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static struct edge_tab edge16_tab[4] = { |
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{ 0xf, 0x8 }, |
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{ 0x7, 0xc }, |
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{ 0x3, 0xe }, |
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{ 0x1, 0xf }, |
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}; |
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static struct edge_tab edge16_tab_l[4] = { |
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{ 0xf, 0x1 }, |
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{ 0xe, 0x3 }, |
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{ 0xc, 0x7 }, |
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{ 0x8, 0xf }, |
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}; |
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static struct edge_tab edge32_tab[2] = { |
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{ 0x3, 0x2 }, |
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{ 0x1, 0x3 }, |
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}; |
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static struct edge_tab edge32_tab_l[2] = { |
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{ 0x3, 0x1 }, |
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{ 0x2, 0x3 }, |
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}; |
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static void edge(struct pt_regs *regs, unsigned int insn, unsigned int opf) |
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{ |
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unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val; |
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u16 left, right; |
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maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); |
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orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); |
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orig_rs2 = rs2 = fetch_reg(RS2(insn), regs); |
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if (test_thread_flag(TIF_32BIT)) { |
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rs1 = rs1 & 0xffffffff; |
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rs2 = rs2 & 0xffffffff; |
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} |
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switch (opf) { |
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default: |
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case EDGE8_OPF: |
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case EDGE8N_OPF: |
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left = edge8_tab[rs1 & 0x7].left; |
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right = edge8_tab[rs2 & 0x7].right; |
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break; |
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case EDGE8L_OPF: |
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case EDGE8LN_OPF: |
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left = edge8_tab_l[rs1 & 0x7].left; |
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right = edge8_tab_l[rs2 & 0x7].right; |
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break; |
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case EDGE16_OPF: |
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case EDGE16N_OPF: |
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left = edge16_tab[(rs1 >> 1) & 0x3].left; |
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right = edge16_tab[(rs2 >> 1) & 0x3].right; |
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break; |
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case EDGE16L_OPF: |
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case EDGE16LN_OPF: |
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left = edge16_tab_l[(rs1 >> 1) & 0x3].left; |
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right = edge16_tab_l[(rs2 >> 1) & 0x3].right; |
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break; |
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case EDGE32_OPF: |
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case EDGE32N_OPF: |
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left = edge32_tab[(rs1 >> 2) & 0x1].left; |
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right = edge32_tab[(rs2 >> 2) & 0x1].right; |
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break; |
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case EDGE32L_OPF: |
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case EDGE32LN_OPF: |
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left = edge32_tab_l[(rs1 >> 2) & 0x1].left; |
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right = edge32_tab_l[(rs2 >> 2) & 0x1].right; |
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break; |
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} |
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if ((rs1 & ~0x7UL) == (rs2 & ~0x7UL)) |
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rd_val = right & left; |
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else |
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rd_val = left; |
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store_reg(regs, rd_val, RD(insn)); |
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switch (opf) { |
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case EDGE8_OPF: |
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case EDGE8L_OPF: |
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case EDGE16_OPF: |
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case EDGE16L_OPF: |
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case EDGE32_OPF: |
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case EDGE32L_OPF: { |
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unsigned long ccr, tstate; |
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__asm__ __volatile__("subcc %1, %2, %%g0\n\t" |
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"rd %%ccr, %0" |
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: "=r" (ccr) |
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: "r" (orig_rs1), "r" (orig_rs2) |
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: "cc"); |
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tstate = regs->tstate & ~(TSTATE_XCC | TSTATE_ICC); |
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regs->tstate = tstate | (ccr << 32UL); |
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} |
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} |
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} |
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static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf) |
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{ |
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unsigned long rs1, rs2, rd_val; |
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unsigned int bits, bits_mask; |
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maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); |
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rs1 = fetch_reg(RS1(insn), regs); |
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rs2 = fetch_reg(RS2(insn), regs); |
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bits = (rs2 > 5 ? 5 : rs2); |
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bits_mask = (1UL << bits) - 1UL; |
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rd_val = ((((rs1 >> 11) & 0x3) << 0) | |
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(((rs1 >> 33) & 0x3) << 2) | |
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(((rs1 >> 55) & 0x1) << 4) | |
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(((rs1 >> 13) & 0xf) << 5) | |
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(((rs1 >> 35) & 0xf) << 9) | |
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(((rs1 >> 56) & 0xf) << 13) | |
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(((rs1 >> 17) & bits_mask) << 17) | |
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(((rs1 >> 39) & bits_mask) << (17 + bits)) | |
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(((rs1 >> 60) & 0xf) << (17 + (2*bits)))); |
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switch (opf) { |
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case ARRAY16_OPF: |
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rd_val <<= 1; |
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break; |
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case ARRAY32_OPF: |
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rd_val <<= 2; |
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} |
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store_reg(regs, rd_val, RD(insn)); |
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} |
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static void bmask(struct pt_regs *regs, unsigned int insn) |
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{ |
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unsigned long rs1, rs2, rd_val, gsr; |
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maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0); |
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rs1 = fetch_reg(RS1(insn), regs); |
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rs2 = fetch_reg(RS2(insn), regs); |
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rd_val = rs1 + rs2; |
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store_reg(regs, rd_val, RD(insn)); |
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gsr = current_thread_info()->gsr[0] & 0xffffffff; |
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gsr |= rd_val << 32UL; |
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current_thread_info()->gsr[0] = gsr; |
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} |
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static void bshuffle(struct pt_regs *regs, unsigned int insn) |
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{ |
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struct fpustate *f = FPUSTATE; |
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unsigned long rs1, rs2, rd_val; |
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unsigned long bmask, i; |
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bmask = current_thread_info()->gsr[0] >> 32UL; |
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rs1 = fpd_regval(f, RS1(insn)); |
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rs2 = fpd_regval(f, RS2(insn)); |
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rd_val = 0UL; |
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for (i = 0; i < 8; i++) { |
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unsigned long which = (bmask >> (i * 4)) & 0xf; |
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unsigned long byte; |
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if (which < 8) |
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byte = (rs1 >> (which * 8)) & 0xff; |
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else |
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byte = (rs2 >> ((which-8)*8)) & 0xff; |
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rd_val |= (byte << (i * 8)); |
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} |
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*fpd_regaddr(f, RD(insn)) = rd_val; |
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} |
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static void pdist(struct pt_regs *regs, unsigned int insn) |
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{ |
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struct fpustate *f = FPUSTATE; |
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unsigned long rs1, rs2, *rd, rd_val; |
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unsigned long i; |
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rs1 = fpd_regval(f, RS1(insn)); |
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rs2 = fpd_regval(f, RS2(insn)); |
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rd = fpd_regaddr(f, RD(insn)); |
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rd_val = *rd; |
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for (i = 0; i < 8; i++) { |
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s16 s1, s2; |
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s1 = (rs1 >> (56 - (i * 8))) & 0xff; |
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s2 = (rs2 >> (56 - (i * 8))) & 0xff; |
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|
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/* Absolute value of difference. */ |
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s1 -= s2; |
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if (s1 < 0) |
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s1 = ~s1 + 1; |
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rd_val += s1; |
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} |
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*rd = rd_val; |
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} |
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static void pformat(struct pt_regs *regs, unsigned int insn, unsigned int opf) |
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{ |
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struct fpustate *f = FPUSTATE; |
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unsigned long rs1, rs2, gsr, scale, rd_val; |
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gsr = current_thread_info()->gsr[0]; |
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scale = (gsr >> 3) & (opf == FPACK16_OPF ? 0xf : 0x1f); |
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switch (opf) { |
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case FPACK16_OPF: { |
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unsigned long byte; |
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rs2 = fpd_regval(f, RS2(insn)); |
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rd_val = 0; |
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for (byte = 0; byte < 4; byte++) { |
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unsigned int val; |
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s16 src = (rs2 >> (byte * 16UL)) & 0xffffUL; |
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int scaled = src << scale; |
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int from_fixed = scaled >> 7; |
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|
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val = ((from_fixed < 0) ? |
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0 : |
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(from_fixed > 255) ? |
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255 : from_fixed); |
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|
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rd_val |= (val << (8 * byte)); |
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} |
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*fps_regaddr(f, RD(insn)) = rd_val; |
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break; |
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} |
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|
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case FPACK32_OPF: { |
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unsigned long word; |
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|
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rs1 = fpd_regval(f, RS1(insn)); |
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rs2 = fpd_regval(f, RS2(insn)); |
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rd_val = (rs1 << 8) & ~(0x000000ff000000ffUL); |
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for (word = 0; word < 2; word++) { |
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unsigned long val; |
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s32 src = (rs2 >> (word * 32UL)); |
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s64 scaled = src << scale; |
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s64 from_fixed = scaled >> 23; |
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|
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val = ((from_fixed < 0) ? |
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0 : |
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(from_fixed > 255) ? |
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255 : from_fixed); |
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|
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rd_val |= (val << (32 * word)); |
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} |
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*fpd_regaddr(f, RD(insn)) = rd_val; |
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break; |
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} |
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|
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case FPACKFIX_OPF: { |
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unsigned long word; |
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|
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rs2 = fpd_regval(f, RS2(insn)); |
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|
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rd_val = 0; |
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for (word = 0; word < 2; word++) { |
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long val; |
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s32 src = (rs2 >> (word * 32UL)); |
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s64 scaled = src << scale; |
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s64 from_fixed = scaled >> 16; |
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|
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val = ((from_fixed < -32768) ? |
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-32768 : |
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(from_fixed > 32767) ? |
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32767 : from_fixed); |
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|
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rd_val |= ((val & 0xffff) << (word * 16)); |
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} |
|
*fps_regaddr(f, RD(insn)) = rd_val; |
|
break; |
|
} |
|
|
|
case FEXPAND_OPF: { |
|
unsigned long byte; |
|
|
|
rs2 = fps_regval(f, RS2(insn)); |
|
|
|
rd_val = 0; |
|
for (byte = 0; byte < 4; byte++) { |
|
unsigned long val; |
|
u8 src = (rs2 >> (byte * 8)) & 0xff; |
|
|
|
val = src << 4; |
|
|
|
rd_val |= (val << (byte * 16)); |
|
} |
|
*fpd_regaddr(f, RD(insn)) = rd_val; |
|
break; |
|
} |
|
|
|
case FPMERGE_OPF: { |
|
rs1 = fps_regval(f, RS1(insn)); |
|
rs2 = fps_regval(f, RS2(insn)); |
|
|
|
rd_val = (((rs2 & 0x000000ff) << 0) | |
|
((rs1 & 0x000000ff) << 8) | |
|
((rs2 & 0x0000ff00) << 8) | |
|
((rs1 & 0x0000ff00) << 16) | |
|
((rs2 & 0x00ff0000) << 16) | |
|
((rs1 & 0x00ff0000) << 24) | |
|
((rs2 & 0xff000000) << 24) | |
|
((rs1 & 0xff000000) << 32)); |
|
*fpd_regaddr(f, RD(insn)) = rd_val; |
|
break; |
|
} |
|
} |
|
} |
|
|
|
static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf) |
|
{ |
|
struct fpustate *f = FPUSTATE; |
|
unsigned long rs1, rs2, rd_val; |
|
|
|
switch (opf) { |
|
case FMUL8x16_OPF: { |
|
unsigned long byte; |
|
|
|
rs1 = fps_regval(f, RS1(insn)); |
|
rs2 = fpd_regval(f, RS2(insn)); |
|
|
|
rd_val = 0; |
|
for (byte = 0; byte < 4; byte++) { |
|
u16 src1 = (rs1 >> (byte * 8)) & 0x00ff; |
|
s16 src2 = (rs2 >> (byte * 16)) & 0xffff; |
|
u32 prod = src1 * src2; |
|
u16 scaled = ((prod & 0x00ffff00) >> 8); |
|
|
|
/* Round up. */ |
|
if (prod & 0x80) |
|
scaled++; |
|
rd_val |= ((scaled & 0xffffUL) << (byte * 16UL)); |
|
} |
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val; |
|
break; |
|
} |
|
|
|
case FMUL8x16AU_OPF: |
|
case FMUL8x16AL_OPF: { |
|
unsigned long byte; |
|
s16 src2; |
|
|
|
rs1 = fps_regval(f, RS1(insn)); |
|
rs2 = fps_regval(f, RS2(insn)); |
|
|
|
rd_val = 0; |
|
src2 = rs2 >> (opf == FMUL8x16AU_OPF ? 16 : 0); |
|
for (byte = 0; byte < 4; byte++) { |
|
u16 src1 = (rs1 >> (byte * 8)) & 0x00ff; |
|
u32 prod = src1 * src2; |
|
u16 scaled = ((prod & 0x00ffff00) >> 8); |
|
|
|
/* Round up. */ |
|
if (prod & 0x80) |
|
scaled++; |
|
rd_val |= ((scaled & 0xffffUL) << (byte * 16UL)); |
|
} |
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val; |
|
break; |
|
} |
|
|
|
case FMUL8SUx16_OPF: |
|
case FMUL8ULx16_OPF: { |
|
unsigned long byte, ushift; |
|
|
|
rs1 = fpd_regval(f, RS1(insn)); |
|
rs2 = fpd_regval(f, RS2(insn)); |
|
|
|
rd_val = 0; |
|
ushift = (opf == FMUL8SUx16_OPF) ? 8 : 0; |
|
for (byte = 0; byte < 4; byte++) { |
|
u16 src1; |
|
s16 src2; |
|
u32 prod; |
|
u16 scaled; |
|
|
|
src1 = ((rs1 >> ((16 * byte) + ushift)) & 0x00ff); |
|
src2 = ((rs2 >> (16 * byte)) & 0xffff); |
|
prod = src1 * src2; |
|
scaled = ((prod & 0x00ffff00) >> 8); |
|
|
|
/* Round up. */ |
|
if (prod & 0x80) |
|
scaled++; |
|
rd_val |= ((scaled & 0xffffUL) << (byte * 16UL)); |
|
} |
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val; |
|
break; |
|
} |
|
|
|
case FMULD8SUx16_OPF: |
|
case FMULD8ULx16_OPF: { |
|
unsigned long byte, ushift; |
|
|
|
rs1 = fps_regval(f, RS1(insn)); |
|
rs2 = fps_regval(f, RS2(insn)); |
|
|
|
rd_val = 0; |
|
ushift = (opf == FMULD8SUx16_OPF) ? 8 : 0; |
|
for (byte = 0; byte < 2; byte++) { |
|
u16 src1; |
|
s16 src2; |
|
u32 prod; |
|
u16 scaled; |
|
|
|
src1 = ((rs1 >> ((16 * byte) + ushift)) & 0x00ff); |
|
src2 = ((rs2 >> (16 * byte)) & 0xffff); |
|
prod = src1 * src2; |
|
scaled = ((prod & 0x00ffff00) >> 8); |
|
|
|
/* Round up. */ |
|
if (prod & 0x80) |
|
scaled++; |
|
rd_val |= ((scaled & 0xffffUL) << |
|
((byte * 32UL) + 7UL)); |
|
} |
|
*fpd_regaddr(f, RD(insn)) = rd_val; |
|
break; |
|
} |
|
} |
|
} |
|
|
|
static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf) |
|
{ |
|
struct fpustate *f = FPUSTATE; |
|
unsigned long rs1, rs2, rd_val, i; |
|
|
|
rs1 = fpd_regval(f, RS1(insn)); |
|
rs2 = fpd_regval(f, RS2(insn)); |
|
|
|
rd_val = 0; |
|
|
|
switch (opf) { |
|
case FCMPGT16_OPF: |
|
for (i = 0; i < 4; i++) { |
|
s16 a = (rs1 >> (i * 16)) & 0xffff; |
|
s16 b = (rs2 >> (i * 16)) & 0xffff; |
|
|
|
if (a > b) |
|
rd_val |= 8 >> i; |
|
} |
|
break; |
|
|
|
case FCMPGT32_OPF: |
|
for (i = 0; i < 2; i++) { |
|
s32 a = (rs1 >> (i * 32)) & 0xffffffff; |
|
s32 b = (rs2 >> (i * 32)) & 0xffffffff; |
|
|
|
if (a > b) |
|
rd_val |= 2 >> i; |
|
} |
|
break; |
|
|
|
case FCMPLE16_OPF: |
|
for (i = 0; i < 4; i++) { |
|
s16 a = (rs1 >> (i * 16)) & 0xffff; |
|
s16 b = (rs2 >> (i * 16)) & 0xffff; |
|
|
|
if (a <= b) |
|
rd_val |= 8 >> i; |
|
} |
|
break; |
|
|
|
case FCMPLE32_OPF: |
|
for (i = 0; i < 2; i++) { |
|
s32 a = (rs1 >> (i * 32)) & 0xffffffff; |
|
s32 b = (rs2 >> (i * 32)) & 0xffffffff; |
|
|
|
if (a <= b) |
|
rd_val |= 2 >> i; |
|
} |
|
break; |
|
|
|
case FCMPNE16_OPF: |
|
for (i = 0; i < 4; i++) { |
|
s16 a = (rs1 >> (i * 16)) & 0xffff; |
|
s16 b = (rs2 >> (i * 16)) & 0xffff; |
|
|
|
if (a != b) |
|
rd_val |= 8 >> i; |
|
} |
|
break; |
|
|
|
case FCMPNE32_OPF: |
|
for (i = 0; i < 2; i++) { |
|
s32 a = (rs1 >> (i * 32)) & 0xffffffff; |
|
s32 b = (rs2 >> (i * 32)) & 0xffffffff; |
|
|
|
if (a != b) |
|
rd_val |= 2 >> i; |
|
} |
|
break; |
|
|
|
case FCMPEQ16_OPF: |
|
for (i = 0; i < 4; i++) { |
|
s16 a = (rs1 >> (i * 16)) & 0xffff; |
|
s16 b = (rs2 >> (i * 16)) & 0xffff; |
|
|
|
if (a == b) |
|
rd_val |= 8 >> i; |
|
} |
|
break; |
|
|
|
case FCMPEQ32_OPF: |
|
for (i = 0; i < 2; i++) { |
|
s32 a = (rs1 >> (i * 32)) & 0xffffffff; |
|
s32 b = (rs2 >> (i * 32)) & 0xffffffff; |
|
|
|
if (a == b) |
|
rd_val |= 2 >> i; |
|
} |
|
break; |
|
} |
|
|
|
maybe_flush_windows(0, 0, RD(insn), 0); |
|
store_reg(regs, rd_val, RD(insn)); |
|
} |
|
|
|
/* Emulate the VIS instructions which are not implemented in |
|
* hardware on Niagara. |
|
*/ |
|
int vis_emul(struct pt_regs *regs, unsigned int insn) |
|
{ |
|
unsigned long pc = regs->tpc; |
|
unsigned int opf; |
|
|
|
BUG_ON(regs->tstate & TSTATE_PRIV); |
|
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); |
|
|
|
if (test_thread_flag(TIF_32BIT)) |
|
pc = (u32)pc; |
|
|
|
if (get_user(insn, (u32 __user *) pc)) |
|
return -EFAULT; |
|
|
|
save_and_clear_fpu(); |
|
|
|
opf = (insn & VIS_OPF_MASK) >> VIS_OPF_SHIFT; |
|
switch (opf) { |
|
default: |
|
return -EINVAL; |
|
|
|
/* Pixel Formatting Instructions. */ |
|
case FPACK16_OPF: |
|
case FPACK32_OPF: |
|
case FPACKFIX_OPF: |
|
case FEXPAND_OPF: |
|
case FPMERGE_OPF: |
|
pformat(regs, insn, opf); |
|
break; |
|
|
|
/* Partitioned Multiply Instructions */ |
|
case FMUL8x16_OPF: |
|
case FMUL8x16AU_OPF: |
|
case FMUL8x16AL_OPF: |
|
case FMUL8SUx16_OPF: |
|
case FMUL8ULx16_OPF: |
|
case FMULD8SUx16_OPF: |
|
case FMULD8ULx16_OPF: |
|
pmul(regs, insn, opf); |
|
break; |
|
|
|
/* Pixel Compare Instructions */ |
|
case FCMPGT16_OPF: |
|
case FCMPGT32_OPF: |
|
case FCMPLE16_OPF: |
|
case FCMPLE32_OPF: |
|
case FCMPNE16_OPF: |
|
case FCMPNE32_OPF: |
|
case FCMPEQ16_OPF: |
|
case FCMPEQ32_OPF: |
|
pcmp(regs, insn, opf); |
|
break; |
|
|
|
/* Edge Handling Instructions */ |
|
case EDGE8_OPF: |
|
case EDGE8N_OPF: |
|
case EDGE8L_OPF: |
|
case EDGE8LN_OPF: |
|
case EDGE16_OPF: |
|
case EDGE16N_OPF: |
|
case EDGE16L_OPF: |
|
case EDGE16LN_OPF: |
|
case EDGE32_OPF: |
|
case EDGE32N_OPF: |
|
case EDGE32L_OPF: |
|
case EDGE32LN_OPF: |
|
edge(regs, insn, opf); |
|
break; |
|
|
|
/* Pixel Component Distance */ |
|
case PDIST_OPF: |
|
pdist(regs, insn); |
|
break; |
|
|
|
/* Three-Dimensional Array Addressing Instructions */ |
|
case ARRAY8_OPF: |
|
case ARRAY16_OPF: |
|
case ARRAY32_OPF: |
|
array(regs, insn, opf); |
|
break; |
|
|
|
/* Byte Mask and Shuffle Instructions */ |
|
case BMASK_OPF: |
|
bmask(regs, insn); |
|
break; |
|
|
|
case BSHUFFLE_OPF: |
|
bshuffle(regs, insn); |
|
break; |
|
} |
|
|
|
regs->tpc = regs->tnpc; |
|
regs->tnpc += 4; |
|
return 0; |
|
}
|
|
|