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356 lines
8.5 KiB
356 lines
8.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* linux/arch/sparc/kernel/time.c |
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* |
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* Copyright (C) 1995 David S. Miller ([email protected]) |
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* Copyright (C) 1996 Thomas K. Dyas ([email protected]) |
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* |
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* Chris Davis ([email protected]) 03/27/1998 |
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* Added support for the intersil on the sun4/4200 |
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* |
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* Gleb Raiko ([email protected]) 08/18/1998 |
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* Support for MicroSPARC-IIep, PCI CPU. |
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* |
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* This file handles the Sparc specific time handling details. |
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* |
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* 1997-09-10 Updated NTP code according to technical memorandum Jan '96 |
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* "A Kernel Model for Precision Timekeeping" by Dave Mills |
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*/ |
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#include <linux/errno.h> |
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#include <linux/module.h> |
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#include <linux/sched.h> |
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#include <linux/kernel.h> |
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#include <linux/param.h> |
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#include <linux/string.h> |
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#include <linux/mm.h> |
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#include <linux/interrupt.h> |
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#include <linux/time.h> |
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#include <linux/rtc/m48t59.h> |
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#include <linux/timex.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/ioport.h> |
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#include <linux/profile.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <asm/mc146818rtc.h> |
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#include <asm/oplib.h> |
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#include <asm/timex.h> |
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#include <asm/timer.h> |
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#include <asm/irq.h> |
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#include <asm/io.h> |
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#include <asm/idprom.h> |
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#include <asm/page.h> |
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#include <asm/pcic.h> |
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#include <asm/irq_regs.h> |
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#include <asm/setup.h> |
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#include "kernel.h" |
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#include "irq.h" |
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static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock); |
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static __volatile__ u64 timer_cs_internal_counter = 0; |
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static char timer_cs_enabled = 0; |
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static struct clock_event_device timer_ce; |
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static char timer_ce_enabled = 0; |
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#ifdef CONFIG_SMP |
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DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent); |
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#endif |
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DEFINE_SPINLOCK(rtc_lock); |
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EXPORT_SYMBOL(rtc_lock); |
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unsigned long profile_pc(struct pt_regs *regs) |
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{ |
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extern char __copy_user_begin[], __copy_user_end[]; |
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extern char __bzero_begin[], __bzero_end[]; |
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unsigned long pc = regs->pc; |
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if (in_lock_functions(pc) || |
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(pc >= (unsigned long) __copy_user_begin && |
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pc < (unsigned long) __copy_user_end) || |
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(pc >= (unsigned long) __bzero_begin && |
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pc < (unsigned long) __bzero_end)) |
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pc = regs->u_regs[UREG_RETPC]; |
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return pc; |
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} |
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EXPORT_SYMBOL(profile_pc); |
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volatile u32 __iomem *master_l10_counter; |
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irqreturn_t notrace timer_interrupt(int dummy, void *dev_id) |
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{ |
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if (timer_cs_enabled) { |
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write_seqlock(&timer_cs_lock); |
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timer_cs_internal_counter++; |
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sparc_config.clear_clock_irq(); |
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write_sequnlock(&timer_cs_lock); |
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} else { |
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sparc_config.clear_clock_irq(); |
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} |
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if (timer_ce_enabled) |
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timer_ce.event_handler(&timer_ce); |
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return IRQ_HANDLED; |
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} |
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static int timer_ce_shutdown(struct clock_event_device *evt) |
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{ |
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timer_ce_enabled = 0; |
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smp_mb(); |
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return 0; |
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} |
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static int timer_ce_set_periodic(struct clock_event_device *evt) |
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{ |
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timer_ce_enabled = 1; |
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smp_mb(); |
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return 0; |
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} |
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static __init void setup_timer_ce(void) |
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{ |
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struct clock_event_device *ce = &timer_ce; |
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BUG_ON(smp_processor_id() != boot_cpu_id); |
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ce->name = "timer_ce"; |
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ce->rating = 100; |
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ce->features = CLOCK_EVT_FEAT_PERIODIC; |
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ce->set_state_shutdown = timer_ce_shutdown; |
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ce->set_state_periodic = timer_ce_set_periodic; |
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ce->tick_resume = timer_ce_set_periodic; |
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ce->cpumask = cpu_possible_mask; |
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ce->shift = 32; |
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ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC, |
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ce->shift); |
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clockevents_register_device(ce); |
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} |
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static unsigned int sbus_cycles_offset(void) |
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{ |
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u32 val, offset; |
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val = sbus_readl(master_l10_counter); |
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offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK; |
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/* Limit hit? */ |
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if (val & TIMER_LIMIT_BIT) |
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offset += sparc_config.cs_period; |
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return offset; |
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} |
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static u64 timer_cs_read(struct clocksource *cs) |
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{ |
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unsigned int seq, offset; |
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u64 cycles; |
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do { |
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seq = read_seqbegin(&timer_cs_lock); |
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cycles = timer_cs_internal_counter; |
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offset = sparc_config.get_cycles_offset(); |
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} while (read_seqretry(&timer_cs_lock, seq)); |
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/* Count absolute cycles */ |
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cycles *= sparc_config.cs_period; |
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cycles += offset; |
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return cycles; |
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} |
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static struct clocksource timer_cs = { |
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.name = "timer_cs", |
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.rating = 100, |
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.read = timer_cs_read, |
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.mask = CLOCKSOURCE_MASK(64), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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static __init int setup_timer_cs(void) |
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{ |
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timer_cs_enabled = 1; |
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return clocksource_register_hz(&timer_cs, sparc_config.clock_rate); |
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} |
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#ifdef CONFIG_SMP |
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static int percpu_ce_shutdown(struct clock_event_device *evt) |
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{ |
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int cpu = cpumask_first(evt->cpumask); |
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sparc_config.load_profile_irq(cpu, 0); |
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return 0; |
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} |
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static int percpu_ce_set_periodic(struct clock_event_device *evt) |
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{ |
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int cpu = cpumask_first(evt->cpumask); |
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sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ); |
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return 0; |
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} |
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static int percpu_ce_set_next_event(unsigned long delta, |
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struct clock_event_device *evt) |
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{ |
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int cpu = cpumask_first(evt->cpumask); |
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unsigned int next = (unsigned int)delta; |
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sparc_config.load_profile_irq(cpu, next); |
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return 0; |
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} |
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void register_percpu_ce(int cpu) |
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{ |
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struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu); |
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unsigned int features = CLOCK_EVT_FEAT_PERIODIC; |
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if (sparc_config.features & FEAT_L14_ONESHOT) |
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features |= CLOCK_EVT_FEAT_ONESHOT; |
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ce->name = "percpu_ce"; |
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ce->rating = 200; |
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ce->features = features; |
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ce->set_state_shutdown = percpu_ce_shutdown; |
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ce->set_state_periodic = percpu_ce_set_periodic; |
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ce->set_state_oneshot = percpu_ce_shutdown; |
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ce->set_next_event = percpu_ce_set_next_event; |
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ce->cpumask = cpumask_of(cpu); |
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ce->shift = 32; |
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ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC, |
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ce->shift); |
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ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce); |
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ce->max_delta_ticks = (unsigned long)sparc_config.clock_rate; |
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ce->min_delta_ns = clockevent_delta2ns(100, ce); |
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ce->min_delta_ticks = 100; |
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clockevents_register_device(ce); |
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} |
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#endif |
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static unsigned char mostek_read_byte(struct device *dev, u32 ofs) |
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{ |
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struct platform_device *pdev = to_platform_device(dev); |
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struct m48t59_plat_data *pdata = pdev->dev.platform_data; |
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return readb(pdata->ioaddr + ofs); |
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} |
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static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) |
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{ |
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struct platform_device *pdev = to_platform_device(dev); |
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struct m48t59_plat_data *pdata = pdev->dev.platform_data; |
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writeb(val, pdata->ioaddr + ofs); |
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} |
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static struct m48t59_plat_data m48t59_data = { |
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.read_byte = mostek_read_byte, |
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.write_byte = mostek_write_byte, |
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}; |
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/* resource is set at runtime */ |
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static struct platform_device m48t59_rtc = { |
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.name = "rtc-m48t59", |
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.id = 0, |
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.num_resources = 1, |
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.dev = { |
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.platform_data = &m48t59_data, |
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}, |
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}; |
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static int clock_probe(struct platform_device *op) |
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{ |
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struct device_node *dp = op->dev.of_node; |
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const char *model = of_get_property(dp, "model", NULL); |
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if (!model) |
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return -ENODEV; |
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/* Only the primary RTC has an address property */ |
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if (!of_find_property(dp, "address", NULL)) |
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return -ENODEV; |
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m48t59_rtc.resource = &op->resource[0]; |
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if (!strcmp(model, "mk48t02")) { |
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/* Map the clock register io area read-only */ |
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m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0, |
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2048, "rtc-m48t59"); |
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m48t59_data.type = M48T59RTC_TYPE_M48T02; |
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} else if (!strcmp(model, "mk48t08")) { |
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m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0, |
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8192, "rtc-m48t59"); |
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m48t59_data.type = M48T59RTC_TYPE_M48T08; |
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} else |
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return -ENODEV; |
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if (platform_device_register(&m48t59_rtc) < 0) |
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printk(KERN_ERR "Registering RTC device failed\n"); |
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return 0; |
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} |
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static const struct of_device_id clock_match[] = { |
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{ |
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.name = "eeprom", |
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}, |
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{}, |
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}; |
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static struct platform_driver clock_driver = { |
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.probe = clock_probe, |
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.driver = { |
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.name = "rtc", |
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.of_match_table = clock_match, |
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}, |
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}; |
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/* Probe for the mostek real time clock chip. */ |
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static int __init clock_init(void) |
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{ |
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return platform_driver_register(&clock_driver); |
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} |
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/* Must be after subsys_initcall() so that busses are probed. Must |
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* be before device_initcall() because things like the RTC driver |
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* need to see the clock registers. |
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*/ |
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fs_initcall(clock_init); |
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static void __init sparc32_late_time_init(void) |
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{ |
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if (sparc_config.features & FEAT_L10_CLOCKEVENT) |
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setup_timer_ce(); |
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if (sparc_config.features & FEAT_L10_CLOCKSOURCE) |
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setup_timer_cs(); |
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#ifdef CONFIG_SMP |
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register_percpu_ce(smp_processor_id()); |
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#endif |
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} |
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static void __init sbus_time_init(void) |
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{ |
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sparc_config.get_cycles_offset = sbus_cycles_offset; |
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sparc_config.init_timers(); |
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} |
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void __init time_init(void) |
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{ |
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sparc_config.features = 0; |
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late_time_init = sparc32_late_time_init; |
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if (pcic_present()) |
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pci_time_init(); |
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else |
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sbus_time_init(); |
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} |
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