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478 lines
14 KiB
478 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* sun4m irq support |
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* |
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* djhr: Hacked out of irq.c into a CPU dependent version. |
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* |
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* Copyright (C) 1995 David S. Miller ([email protected]) |
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* Copyright (C) 1995 Miguel de Icaza ([email protected]) |
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* Copyright (C) 1995 Pete A. Zaitcev ([email protected]) |
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* Copyright (C) 1996 Dave Redman ([email protected]) |
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*/ |
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#include <linux/slab.h> |
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#include <linux/sched/debug.h> |
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#include <linux/pgtable.h> |
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#include <asm/timer.h> |
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#include <asm/traps.h> |
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#include <asm/irq.h> |
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#include <asm/io.h> |
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#include <asm/cacheflush.h> |
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#include "irq.h" |
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#include "kernel.h" |
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|
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/* Sample sun4m IRQ layout: |
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* |
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* 0x22 - Power |
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* 0x24 - ESP SCSI |
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* 0x26 - Lance ethernet |
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* 0x2b - Floppy |
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* 0x2c - Zilog uart |
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* 0x32 - SBUS level 0 |
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* 0x33 - Parallel port, SBUS level 1 |
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* 0x35 - SBUS level 2 |
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* 0x37 - SBUS level 3 |
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* 0x39 - Audio, Graphics card, SBUS level 4 |
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* 0x3b - SBUS level 5 |
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* 0x3d - SBUS level 6 |
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* |
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* Each interrupt source has a mask bit in the interrupt registers. |
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* When the mask bit is set, this blocks interrupt deliver. So you |
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* clear the bit to enable the interrupt. |
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* |
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* Interrupts numbered less than 0x10 are software triggered interrupts |
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* and unused by Linux. |
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* |
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* Interrupt level assignment on sun4m: |
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* |
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* level source |
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* ------------------------------------------------------------ |
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* 1 softint-1 |
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* 2 softint-2, VME/SBUS level 1 |
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* 3 softint-3, VME/SBUS level 2 |
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* 4 softint-4, onboard SCSI |
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* 5 softint-5, VME/SBUS level 3 |
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* 6 softint-6, onboard ETHERNET |
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* 7 softint-7, VME/SBUS level 4 |
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* 8 softint-8, onboard VIDEO |
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* 9 softint-9, VME/SBUS level 5, Module Interrupt |
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* 10 softint-10, system counter/timer |
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* 11 softint-11, VME/SBUS level 6, Floppy |
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* 12 softint-12, Keyboard/Mouse, Serial |
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* 13 softint-13, VME/SBUS level 7, ISDN Audio |
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* 14 softint-14, per-processor counter/timer |
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* 15 softint-15, Asynchronous Errors (broadcast) |
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* |
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* Each interrupt source is masked distinctly in the sun4m interrupt |
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* registers. The PIL level alone is therefore ambiguous, since multiple |
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* interrupt sources map to a single PIL. |
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* |
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* This ambiguity is resolved in the 'intr' property for device nodes |
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* in the OF device tree. Each 'intr' property entry is composed of |
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* two 32-bit words. The first word is the IRQ priority value, which |
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* is what we're intersted in. The second word is the IRQ vector, which |
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* is unused. |
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* |
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* The low 4 bits of the IRQ priority indicate the PIL, and the upper |
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* 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20 |
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* means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled. |
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* |
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* For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI |
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* whereas a value of 0x33 is SBUS level 2. Here are some sample |
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* 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and |
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* Tadpole S3 GX systems. |
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* |
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* esp: 0x24 onboard ESP SCSI |
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* le: 0x26 onboard Lance ETHERNET |
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* p9100: 0x32 SBUS level 1 P9100 video |
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* bpp: 0x33 SBUS level 2 BPP parallel port device |
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* DBRI: 0x39 SBUS level 5 DBRI ISDN audio |
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* SUNW,leo: 0x39 SBUS level 5 LEO video |
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* pcmcia: 0x3b SBUS level 6 PCMCIA controller |
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* uctrl: 0x3b SBUS level 6 UCTRL device |
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* modem: 0x3d SBUS level 7 MODEM |
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* zs: 0x2c onboard keyboard/mouse/serial |
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* floppy: 0x2b onboard Floppy |
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* power: 0x22 onboard power device (XXX unknown mask bit XXX) |
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*/ |
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/* Code in entry.S needs to get at these register mappings. */ |
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struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS]; |
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struct sun4m_irq_global __iomem *sun4m_irq_global; |
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struct sun4m_handler_data { |
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bool percpu; |
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long mask; |
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}; |
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/* Dave Redman ([email protected]) |
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* The sun4m interrupt registers. |
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*/ |
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#define SUN4M_INT_ENABLE 0x80000000 |
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#define SUN4M_INT_E14 0x00000080 |
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#define SUN4M_INT_E10 0x00080000 |
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#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ |
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#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ |
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#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */ |
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#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */ |
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#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */ |
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#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */ |
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#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */ |
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#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */ |
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#define SUN4M_INT_REALTIME 0x00080000 /* system timer */ |
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#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */ |
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#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */ |
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#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */ |
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#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */ |
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#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */ |
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#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */ |
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#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */ |
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#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \ |
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SUN4M_INT_M2S_WRITE_ERR | \ |
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SUN4M_INT_ECC_ERR | \ |
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SUN4M_INT_VME_ERR) |
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#define SUN4M_INT_SBUS(x) (1 << (x+7)) |
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#define SUN4M_INT_VME(x) (1 << (x)) |
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/* Interrupt levels used by OBP */ |
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#define OBP_INT_LEVEL_SOFT 0x10 |
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#define OBP_INT_LEVEL_ONBOARD 0x20 |
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#define OBP_INT_LEVEL_SBUS 0x30 |
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#define OBP_INT_LEVEL_VME 0x40 |
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#define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10) |
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#define SUN4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14) |
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static unsigned long sun4m_imask[0x50] = { |
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/* 0x00 - SMP */ |
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0, SUN4M_SOFT_INT(1), |
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SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3), |
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SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5), |
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SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7), |
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SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9), |
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SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11), |
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SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13), |
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SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15), |
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/* 0x10 - soft */ |
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0, SUN4M_SOFT_INT(1), |
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SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3), |
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SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5), |
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SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7), |
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SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9), |
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SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11), |
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SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13), |
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SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15), |
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/* 0x20 - onboard */ |
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0, 0, 0, 0, |
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SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0, |
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SUN4M_INT_VIDEO, SUN4M_INT_MODULE, |
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SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY, |
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(SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), |
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SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR, |
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/* 0x30 - sbus */ |
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0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1), |
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0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3), |
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0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5), |
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0, SUN4M_INT_SBUS(6), 0, 0, |
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/* 0x40 - vme */ |
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0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1), |
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0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3), |
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0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5), |
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0, SUN4M_INT_VME(6), 0, 0 |
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}; |
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static void sun4m_mask_irq(struct irq_data *data) |
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{ |
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struct sun4m_handler_data *handler_data; |
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int cpu = smp_processor_id(); |
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handler_data = irq_data_get_irq_handler_data(data); |
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if (handler_data->mask) { |
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unsigned long flags; |
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local_irq_save(flags); |
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if (handler_data->percpu) { |
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sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set); |
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} else { |
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sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set); |
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} |
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local_irq_restore(flags); |
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} |
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} |
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static void sun4m_unmask_irq(struct irq_data *data) |
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{ |
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struct sun4m_handler_data *handler_data; |
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int cpu = smp_processor_id(); |
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handler_data = irq_data_get_irq_handler_data(data); |
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if (handler_data->mask) { |
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unsigned long flags; |
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local_irq_save(flags); |
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if (handler_data->percpu) { |
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sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear); |
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} else { |
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sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear); |
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} |
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local_irq_restore(flags); |
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} |
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} |
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static unsigned int sun4m_startup_irq(struct irq_data *data) |
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{ |
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irq_link(data->irq); |
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sun4m_unmask_irq(data); |
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return 0; |
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} |
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static void sun4m_shutdown_irq(struct irq_data *data) |
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{ |
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sun4m_mask_irq(data); |
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irq_unlink(data->irq); |
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} |
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static struct irq_chip sun4m_irq = { |
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.name = "sun4m", |
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.irq_startup = sun4m_startup_irq, |
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.irq_shutdown = sun4m_shutdown_irq, |
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.irq_mask = sun4m_mask_irq, |
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.irq_unmask = sun4m_unmask_irq, |
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}; |
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static unsigned int sun4m_build_device_irq(struct platform_device *op, |
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unsigned int real_irq) |
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{ |
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struct sun4m_handler_data *handler_data; |
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unsigned int irq; |
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unsigned int pil; |
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if (real_irq >= OBP_INT_LEVEL_VME) { |
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prom_printf("Bogus sun4m IRQ %u\n", real_irq); |
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prom_halt(); |
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} |
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pil = (real_irq & 0xf); |
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irq = irq_alloc(real_irq, pil); |
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if (irq == 0) |
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goto out; |
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handler_data = irq_get_handler_data(irq); |
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if (unlikely(handler_data)) |
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goto out; |
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handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC); |
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if (unlikely(!handler_data)) { |
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prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n"); |
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prom_halt(); |
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} |
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handler_data->mask = sun4m_imask[real_irq]; |
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handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD; |
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irq_set_chip_and_handler_name(irq, &sun4m_irq, |
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handle_level_irq, "level"); |
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irq_set_handler_data(irq, handler_data); |
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out: |
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return irq; |
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} |
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struct sun4m_timer_percpu { |
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u32 l14_limit; |
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u32 l14_count; |
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u32 l14_limit_noclear; |
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u32 user_timer_start_stop; |
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}; |
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static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS]; |
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struct sun4m_timer_global { |
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u32 l10_limit; |
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u32 l10_count; |
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u32 l10_limit_noclear; |
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u32 reserved; |
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u32 timer_config; |
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}; |
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static struct sun4m_timer_global __iomem *timers_global; |
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static void sun4m_clear_clock_irq(void) |
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{ |
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sbus_readl(&timers_global->l10_limit); |
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} |
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void sun4m_nmi(struct pt_regs *regs) |
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{ |
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unsigned long afsr, afar, si; |
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printk(KERN_ERR "Aieee: sun4m NMI received!\n"); |
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/* XXX HyperSparc hack XXX */ |
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__asm__ __volatile__("mov 0x500, %%g1\n\t" |
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"lda [%%g1] 0x4, %0\n\t" |
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"mov 0x600, %%g1\n\t" |
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"lda [%%g1] 0x4, %1\n\t" : |
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"=r" (afsr), "=r" (afar)); |
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printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar); |
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si = sbus_readl(&sun4m_irq_global->pending); |
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printk(KERN_ERR "si=%08lx\n", si); |
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if (si & SUN4M_INT_MODULE_ERR) |
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printk(KERN_ERR "Module async error\n"); |
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if (si & SUN4M_INT_M2S_WRITE_ERR) |
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printk(KERN_ERR "MBus/SBus async error\n"); |
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if (si & SUN4M_INT_ECC_ERR) |
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printk(KERN_ERR "ECC memory error\n"); |
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if (si & SUN4M_INT_VME_ERR) |
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printk(KERN_ERR "VME async error\n"); |
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printk(KERN_ERR "you lose buddy boy...\n"); |
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show_regs(regs); |
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prom_halt(); |
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} |
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void sun4m_unmask_profile_irq(void) |
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{ |
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unsigned long flags; |
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local_irq_save(flags); |
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sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear); |
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local_irq_restore(flags); |
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} |
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void sun4m_clear_profile_irq(int cpu) |
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{ |
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sbus_readl(&timers_percpu[cpu]->l14_limit); |
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} |
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static void sun4m_load_profile_irq(int cpu, unsigned int limit) |
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{ |
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unsigned int value = limit ? timer_value(limit) : 0; |
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sbus_writel(value, &timers_percpu[cpu]->l14_limit); |
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} |
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static void __init sun4m_init_timers(void) |
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{ |
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struct device_node *dp = of_find_node_by_name(NULL, "counter"); |
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int i, err, len, num_cpu_timers; |
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unsigned int irq; |
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const u32 *addr; |
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if (!dp) { |
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printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n"); |
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return; |
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} |
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addr = of_get_property(dp, "address", &len); |
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of_node_put(dp); |
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if (!addr) { |
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printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n"); |
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return; |
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} |
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num_cpu_timers = (len / sizeof(u32)) - 1; |
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for (i = 0; i < num_cpu_timers; i++) { |
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timers_percpu[i] = (void __iomem *) |
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(unsigned long) addr[i]; |
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} |
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timers_global = (void __iomem *) |
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(unsigned long) addr[num_cpu_timers]; |
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/* Every per-cpu timer works in timer mode */ |
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sbus_writel(0x00000000, &timers_global->timer_config); |
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#ifdef CONFIG_SMP |
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sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */ |
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sparc_config.features |= FEAT_L14_ONESHOT; |
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#else |
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sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */ |
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sparc_config.features |= FEAT_L10_CLOCKEVENT; |
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#endif |
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sparc_config.features |= FEAT_L10_CLOCKSOURCE; |
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sbus_writel(timer_value(sparc_config.cs_period), |
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&timers_global->l10_limit); |
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master_l10_counter = &timers_global->l10_count; |
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irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ); |
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err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); |
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if (err) { |
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printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n", |
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err); |
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return; |
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} |
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for (i = 0; i < num_cpu_timers; i++) |
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sbus_writel(0, &timers_percpu[i]->l14_limit); |
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if (num_cpu_timers == 4) |
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sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set); |
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#ifdef CONFIG_SMP |
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{ |
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unsigned long flags; |
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struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)]; |
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/* For SMP we use the level 14 ticker, however the bootup code |
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* has copied the firmware's level 14 vector into the boot cpu's |
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* trap table, we must fix this now or we get squashed. |
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*/ |
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local_irq_save(flags); |
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trap_table->inst_one = lvl14_save[0]; |
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trap_table->inst_two = lvl14_save[1]; |
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trap_table->inst_three = lvl14_save[2]; |
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trap_table->inst_four = lvl14_save[3]; |
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local_ops->cache_all(); |
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local_irq_restore(flags); |
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} |
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#endif |
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} |
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void __init sun4m_init_IRQ(void) |
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{ |
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struct device_node *dp = of_find_node_by_name(NULL, "interrupt"); |
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int len, i, mid, num_cpu_iregs; |
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const u32 *addr; |
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if (!dp) { |
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printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n"); |
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return; |
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} |
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addr = of_get_property(dp, "address", &len); |
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of_node_put(dp); |
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if (!addr) { |
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printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n"); |
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return; |
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} |
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num_cpu_iregs = (len / sizeof(u32)) - 1; |
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for (i = 0; i < num_cpu_iregs; i++) { |
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sun4m_irq_percpu[i] = (void __iomem *) |
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(unsigned long) addr[i]; |
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} |
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sun4m_irq_global = (void __iomem *) |
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(unsigned long) addr[num_cpu_iregs]; |
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local_irq_disable(); |
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sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set); |
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for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++) |
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sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear); |
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if (num_cpu_iregs == 4) |
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sbus_writel(0, &sun4m_irq_global->interrupt_target); |
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sparc_config.init_timers = sun4m_init_timers; |
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sparc_config.build_device_irq = sun4m_build_device_irq; |
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sparc_config.clock_rate = SBUS_CLOCK_RATE; |
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sparc_config.clear_clock_irq = sun4m_clear_clock_irq; |
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sparc_config.load_profile_irq = sun4m_load_profile_irq; |
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/* Cannot enable interrupts until OBP ticker is disabled. */ |
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}
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