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841 lines
21 KiB
841 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* pcic.c: MicroSPARC-IIep PCI controller support |
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* |
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* Copyright (C) 1998 V. Roganov and G. Raiko |
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* |
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* Code is derived from Ultra/PCI PSYCHO controller support, see that |
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* for author info. |
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* |
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* Support for diverse IIep based platforms by Pete Zaitcev. |
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* CP-1200 by Eric Brower. |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/init.h> |
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#include <linux/mm.h> |
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#include <linux/slab.h> |
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#include <linux/jiffies.h> |
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#include <asm/swift.h> /* for cache flushing. */ |
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#include <asm/io.h> |
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#include <linux/ctype.h> |
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#include <linux/pci.h> |
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#include <linux/time.h> |
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#include <linux/timex.h> |
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#include <linux/interrupt.h> |
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#include <linux/export.h> |
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#include <asm/irq.h> |
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#include <asm/oplib.h> |
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#include <asm/prom.h> |
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#include <asm/pcic.h> |
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#include <asm/timex.h> |
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#include <asm/timer.h> |
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#include <linux/uaccess.h> |
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#include <asm/irq_regs.h> |
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#include "kernel.h" |
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#include "irq.h" |
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|
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/* |
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* I studied different documents and many live PROMs both from 2.30 |
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* family and 3.xx versions. I came to the amazing conclusion: there is |
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* absolutely no way to route interrupts in IIep systems relying on |
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* information which PROM presents. We must hardcode interrupt routing |
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* schematics. And this actually sucks. -- zaitcev 1999/05/12 |
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* |
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* To find irq for a device we determine which routing map |
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* is in effect or, in other words, on which machine we are running. |
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* We use PROM name for this although other techniques may be used |
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* in special cases (Gleb reports a PROMless IIep based system). |
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* Once we know the map we take device configuration address and |
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* find PCIC pin number where INT line goes. Then we may either program |
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* preferred irq into the PCIC or supply the preexisting irq to the device. |
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*/ |
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struct pcic_ca2irq { |
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unsigned char busno; /* PCI bus number */ |
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unsigned char devfn; /* Configuration address */ |
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unsigned char pin; /* PCIC external interrupt pin */ |
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unsigned char irq; /* Preferred IRQ (mappable in PCIC) */ |
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unsigned int force; /* Enforce preferred IRQ */ |
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}; |
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struct pcic_sn2list { |
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char *sysname; |
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struct pcic_ca2irq *intmap; |
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int mapdim; |
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}; |
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/* |
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* JavaEngine-1 apparently has different versions. |
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* |
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* According to communications with Sun folks, for P2 build 501-4628-03: |
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* pin 0 - parallel, audio; |
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* pin 1 - Ethernet; |
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* pin 2 - su; |
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* pin 3 - PS/2 kbd and mouse. |
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* |
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* OEM manual (805-1486): |
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* pin 0: Ethernet |
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* pin 1: All EBus |
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* pin 2: IGA (unused) |
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* pin 3: Not connected |
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* OEM manual says that 501-4628 & 501-4811 are the same thing, |
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* only the latter has NAND flash in place. |
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* |
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* So far unofficial Sun wins over the OEM manual. Poor OEMs... |
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*/ |
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static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */ |
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{ 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */ |
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{ 0, 0x01, 1, 6, 1 }, /* Happy Meal */ |
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{ 0, 0x80, 0, 7, 0 }, /* IGA (unused) */ |
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}; |
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/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */ |
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static struct pcic_ca2irq pcic_i_jse[] = { |
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{ 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ |
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{ 0, 0x01, 1, 6, 0 }, /* hme */ |
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{ 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */ |
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{ 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */ |
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{ 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */ |
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{ 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */ |
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{ 0, 0x80, 5, 11, 0 }, /* EIDE */ |
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/* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */ |
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{ 0, 0xA0, 4, 9, 0 }, /* USB */ |
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/* |
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* Some pins belong to non-PCI devices, we hardcode them in drivers. |
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* sun4m timers - irq 10, 14 |
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* PC style RTC - pin 7, irq 4 ? |
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* Smart card, Parallel - pin 4 shared with USB, ISA |
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* audio - pin 3, irq 5 ? |
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*/ |
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}; |
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/* SPARCengine-6 was the original release name of CP1200. |
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* The documentation differs between the two versions |
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*/ |
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static struct pcic_ca2irq pcic_i_se6[] = { |
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{ 0, 0x08, 0, 2, 0 }, /* SCSI */ |
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{ 0, 0x01, 1, 6, 0 }, /* HME */ |
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{ 0, 0x00, 3, 13, 0 }, /* EBus */ |
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}; |
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/* |
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* Krups (courtesy of Varol Kaptan) |
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* No documentation available, but it was easy to guess |
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* because it was very similar to Espresso. |
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* |
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* pin 0 - kbd, mouse, serial; |
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* pin 1 - Ethernet; |
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* pin 2 - igs (we do not use it); |
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* pin 3 - audio; |
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* pin 4,5,6 - unused; |
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* pin 7 - RTC (from P2 onwards as David B. says). |
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*/ |
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static struct pcic_ca2irq pcic_i_jk[] = { |
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{ 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ |
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{ 0, 0x01, 1, 6, 0 }, /* hme */ |
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}; |
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/* |
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* Several entries in this list may point to the same routing map |
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* as several PROMs may be installed on the same physical board. |
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*/ |
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#define SN2L_INIT(name, map) \ |
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{ name, map, ARRAY_SIZE(map) } |
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static struct pcic_sn2list pcic_known_sysnames[] = { |
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SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */ |
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SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */ |
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SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */ |
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SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */ |
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SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */ |
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{ NULL, NULL, 0 } |
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}; |
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/* |
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* Only one PCIC per IIep, |
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* and since we have no SMP IIep, only one per system. |
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*/ |
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static int pcic0_up; |
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static struct linux_pcic pcic0; |
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void __iomem *pcic_regs; |
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static volatile int pcic_speculative; |
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static volatile int pcic_trapped; |
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/* forward */ |
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unsigned int pcic_build_device_irq(struct platform_device *op, |
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unsigned int real_irq); |
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#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3)) |
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static int pcic_read_config_dword(unsigned int busno, unsigned int devfn, |
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int where, u32 *value) |
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{ |
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struct linux_pcic *pcic; |
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unsigned long flags; |
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pcic = &pcic0; |
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local_irq_save(flags); |
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#if 0 /* does not fail here */ |
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pcic_speculative = 1; |
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pcic_trapped = 0; |
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#endif |
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writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr); |
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#if 0 /* does not fail here */ |
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nop(); |
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if (pcic_trapped) { |
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local_irq_restore(flags); |
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*value = ~0; |
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return 0; |
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} |
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#endif |
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pcic_speculative = 2; |
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pcic_trapped = 0; |
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*value = readl(pcic->pcic_config_space_data + (where&4)); |
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nop(); |
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if (pcic_trapped) { |
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pcic_speculative = 0; |
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local_irq_restore(flags); |
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*value = ~0; |
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return 0; |
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} |
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pcic_speculative = 0; |
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local_irq_restore(flags); |
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return 0; |
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} |
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static int pcic_read_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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unsigned int v; |
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if (bus->number != 0) return -EINVAL; |
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switch (size) { |
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case 1: |
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pcic_read_config_dword(bus->number, devfn, where&~3, &v); |
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*val = 0xff & (v >> (8*(where & 3))); |
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return 0; |
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case 2: |
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if (where&1) return -EINVAL; |
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pcic_read_config_dword(bus->number, devfn, where&~3, &v); |
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*val = 0xffff & (v >> (8*(where & 3))); |
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return 0; |
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case 4: |
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if (where&3) return -EINVAL; |
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pcic_read_config_dword(bus->number, devfn, where&~3, val); |
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return 0; |
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} |
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return -EINVAL; |
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} |
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static int pcic_write_config_dword(unsigned int busno, unsigned int devfn, |
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int where, u32 value) |
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{ |
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struct linux_pcic *pcic; |
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unsigned long flags; |
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pcic = &pcic0; |
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local_irq_save(flags); |
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writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr); |
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writel(value, pcic->pcic_config_space_data + (where&4)); |
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local_irq_restore(flags); |
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return 0; |
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} |
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static int pcic_write_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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unsigned int v; |
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if (bus->number != 0) return -EINVAL; |
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switch (size) { |
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case 1: |
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pcic_read_config_dword(bus->number, devfn, where&~3, &v); |
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v = (v & ~(0xff << (8*(where&3)))) | |
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((0xff&val) << (8*(where&3))); |
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return pcic_write_config_dword(bus->number, devfn, where&~3, v); |
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case 2: |
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if (where&1) return -EINVAL; |
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pcic_read_config_dword(bus->number, devfn, where&~3, &v); |
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v = (v & ~(0xffff << (8*(where&3)))) | |
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((0xffff&val) << (8*(where&3))); |
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return pcic_write_config_dword(bus->number, devfn, where&~3, v); |
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case 4: |
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if (where&3) return -EINVAL; |
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return pcic_write_config_dword(bus->number, devfn, where, val); |
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} |
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return -EINVAL; |
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} |
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static struct pci_ops pcic_ops = { |
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.read = pcic_read_config, |
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.write = pcic_write_config, |
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}; |
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/* |
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* On sparc64 pcibios_init() calls pci_controller_probe(). |
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* We want PCIC probed little ahead so that interrupt controller |
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* would be operational. |
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*/ |
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int __init pcic_probe(void) |
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{ |
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struct linux_pcic *pcic; |
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struct linux_prom_registers regs[PROMREG_MAX]; |
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struct linux_pbm_info* pbm; |
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char namebuf[64]; |
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phandle node; |
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int err; |
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if (pcic0_up) { |
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prom_printf("PCIC: called twice!\n"); |
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prom_halt(); |
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} |
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pcic = &pcic0; |
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node = prom_getchild (prom_root_node); |
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node = prom_searchsiblings (node, "pci"); |
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if (node == 0) |
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return -ENODEV; |
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/* |
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* Map in PCIC register set, config space, and IO base |
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*/ |
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err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs)); |
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if (err == 0 || err == -1) { |
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prom_printf("PCIC: Error, cannot get PCIC registers " |
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"from PROM.\n"); |
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prom_halt(); |
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} |
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pcic0_up = 1; |
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pcic->pcic_res_regs.name = "pcic_registers"; |
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pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size); |
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if (!pcic->pcic_regs) { |
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prom_printf("PCIC: Error, cannot map PCIC registers.\n"); |
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prom_halt(); |
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} |
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pcic->pcic_res_io.name = "pcic_io"; |
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if ((pcic->pcic_io = (unsigned long) |
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ioremap(regs[1].phys_addr, 0x10000)) == 0) { |
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prom_printf("PCIC: Error, cannot map PCIC IO Base.\n"); |
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prom_halt(); |
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} |
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pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr"; |
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if ((pcic->pcic_config_space_addr = |
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ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) { |
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prom_printf("PCIC: Error, cannot map " |
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"PCI Configuration Space Address.\n"); |
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prom_halt(); |
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} |
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/* |
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* Docs say three least significant bits in address and data |
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* must be the same. Thus, we need adjust size of data. |
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*/ |
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pcic->pcic_res_cfg_data.name = "pcic_cfg_data"; |
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if ((pcic->pcic_config_space_data = |
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ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) { |
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prom_printf("PCIC: Error, cannot map " |
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"PCI Configuration Space Data.\n"); |
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prom_halt(); |
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} |
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pbm = &pcic->pbm; |
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pbm->prom_node = node; |
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prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; |
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strcpy(pbm->prom_name, namebuf); |
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{ |
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extern int pcic_nmi_trap_patch[4]; |
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t_nmi[0] = pcic_nmi_trap_patch[0]; |
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t_nmi[1] = pcic_nmi_trap_patch[1]; |
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t_nmi[2] = pcic_nmi_trap_patch[2]; |
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t_nmi[3] = pcic_nmi_trap_patch[3]; |
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swift_flush_dcache(); |
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pcic_regs = pcic->pcic_regs; |
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} |
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prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0; |
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{ |
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struct pcic_sn2list *p; |
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for (p = pcic_known_sysnames; p->sysname != NULL; p++) { |
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if (strcmp(namebuf, p->sysname) == 0) |
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break; |
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} |
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pcic->pcic_imap = p->intmap; |
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pcic->pcic_imdim = p->mapdim; |
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} |
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if (pcic->pcic_imap == NULL) { |
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/* |
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* We do not panic here for the sake of embedded systems. |
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*/ |
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printk("PCIC: System %s is unknown, cannot route interrupts\n", |
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namebuf); |
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} |
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return 0; |
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} |
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static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic) |
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{ |
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struct linux_pbm_info *pbm = &pcic->pbm; |
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pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm); |
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if (!pbm->pci_bus) |
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return; |
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#if 0 /* deadwood transplanted from sparc64 */ |
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pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node); |
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pci_record_assignments(pbm, pbm->pci_bus); |
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pci_assign_unassigned(pbm, pbm->pci_bus); |
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pci_fixup_irq(pbm, pbm->pci_bus); |
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#endif |
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pci_bus_add_devices(pbm->pci_bus); |
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} |
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/* |
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* Main entry point from the PCI subsystem. |
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*/ |
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static int __init pcic_init(void) |
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{ |
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struct linux_pcic *pcic; |
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/* |
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* PCIC should be initialized at start of the timer. |
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* So, here we report the presence of PCIC and do some magic passes. |
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*/ |
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if(!pcic0_up) |
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return 0; |
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pcic = &pcic0; |
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/* |
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* Switch off IOTLB translation. |
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*/ |
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writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE, |
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pcic->pcic_regs+PCI_DVMA_CONTROL); |
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/* |
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* Increase mapped size for PCI memory space (DMA access). |
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* Should be done in that order (size first, address second). |
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* Why we couldn't set up 4GB and forget about it? XXX |
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*/ |
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writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0); |
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writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY, |
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pcic->pcic_regs+PCI_BASE_ADDRESS_0); |
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pcic_pbm_scan_bus(pcic); |
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return 0; |
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} |
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int pcic_present(void) |
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{ |
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return pcic0_up; |
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} |
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static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev) |
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{ |
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struct linux_prom_pci_registers regs[PROMREG_MAX]; |
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int err; |
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phandle node = prom_getchild(pbm->prom_node); |
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while(node) { |
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err = prom_getproperty(node, "reg", |
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(char *)®s[0], sizeof(regs)); |
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if(err != 0 && err != -1) { |
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unsigned long devfn = (regs[0].which_io >> 8) & 0xff; |
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if(devfn == pdev->devfn) |
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return node; |
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} |
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node = prom_getsibling(node); |
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} |
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return 0; |
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} |
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static inline struct pcidev_cookie *pci_devcookie_alloc(void) |
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{ |
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return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC); |
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} |
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static void pcic_map_pci_device(struct linux_pcic *pcic, |
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struct pci_dev *dev, int node) |
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{ |
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char namebuf[64]; |
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unsigned long address; |
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unsigned long flags; |
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int j; |
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if (node == 0 || node == -1) { |
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strcpy(namebuf, "???"); |
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} else { |
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prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; |
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} |
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for (j = 0; j < 6; j++) { |
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address = dev->resource[j].start; |
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if (address == 0) break; /* are sequential */ |
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flags = dev->resource[j].flags; |
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if ((flags & IORESOURCE_IO) != 0) { |
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if (address < 0x10000) { |
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/* |
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* A device responds to I/O cycles on PCI. |
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* We generate these cycles with memory |
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* access into the fixed map (phys 0x30000000). |
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* |
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* Since a device driver does not want to |
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* do ioremap() before accessing PC-style I/O, |
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* we supply virtual, ready to access address. |
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* |
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* Note that request_region() |
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* works for these devices. |
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* |
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* XXX Neat trick, but it's a *bad* idea |
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* to shit into regions like that. |
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* What if we want to allocate one more |
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* PCI base address... |
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*/ |
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dev->resource[j].start = |
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pcic->pcic_io + address; |
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dev->resource[j].end = 1; /* XXX */ |
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dev->resource[j].flags = |
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(flags & ~IORESOURCE_IO) | IORESOURCE_MEM; |
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} else { |
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/* |
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* OOPS... PCI Spec allows this. Sun does |
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* not have any devices getting above 64K |
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* so it must be user with a weird I/O |
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* board in a PCI slot. We must remap it |
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* under 64K but it is not done yet. XXX |
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*/ |
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pci_info(dev, "PCIC: Skipping I/O space at " |
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"0x%lx, this will Oops if a driver " |
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"attaches device '%s'\n", address, |
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namebuf); |
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} |
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} |
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} |
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} |
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|
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static void |
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pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node) |
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{ |
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struct pcic_ca2irq *p; |
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unsigned int real_irq; |
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int i, ivec; |
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char namebuf[64]; |
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|
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if (node == 0 || node == -1) { |
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strcpy(namebuf, "???"); |
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} else { |
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prom_getstring(node, "name", namebuf, sizeof(namebuf)); |
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} |
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|
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if ((p = pcic->pcic_imap) == NULL) { |
|
dev->irq = 0; |
|
return; |
|
} |
|
for (i = 0; i < pcic->pcic_imdim; i++) { |
|
if (p->busno == dev->bus->number && p->devfn == dev->devfn) |
|
break; |
|
p++; |
|
} |
|
if (i >= pcic->pcic_imdim) { |
|
pci_info(dev, "PCIC: device %s not found in %d\n", namebuf, |
|
pcic->pcic_imdim); |
|
dev->irq = 0; |
|
return; |
|
} |
|
|
|
i = p->pin; |
|
if (i >= 0 && i < 4) { |
|
ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); |
|
real_irq = ivec >> (i << 2) & 0xF; |
|
} else if (i >= 4 && i < 8) { |
|
ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); |
|
real_irq = ivec >> ((i-4) << 2) & 0xF; |
|
} else { /* Corrupted map */ |
|
pci_info(dev, "PCIC: BAD PIN %d\n", i); for (;;) {} |
|
} |
|
/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */ |
|
|
|
/* real_irq means PROM did not bother to program the upper |
|
* half of PCIC. This happens on JS-E with PROM 3.11, for instance. |
|
*/ |
|
if (real_irq == 0 || p->force) { |
|
if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */ |
|
pci_info(dev, "PCIC: BAD IRQ %d\n", p->irq); for (;;) {} |
|
} |
|
pci_info(dev, "PCIC: setting irq %d at pin %d\n", p->irq, |
|
p->pin); |
|
real_irq = p->irq; |
|
|
|
i = p->pin; |
|
if (i >= 4) { |
|
ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); |
|
ivec &= ~(0xF << ((i - 4) << 2)); |
|
ivec |= p->irq << ((i - 4) << 2); |
|
writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI); |
|
} else { |
|
ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); |
|
ivec &= ~(0xF << (i << 2)); |
|
ivec |= p->irq << (i << 2); |
|
writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO); |
|
} |
|
} |
|
dev->irq = pcic_build_device_irq(NULL, real_irq); |
|
} |
|
|
|
/* |
|
* Normally called from {do_}pci_scan_bus... |
|
*/ |
|
void pcibios_fixup_bus(struct pci_bus *bus) |
|
{ |
|
struct pci_dev *dev; |
|
struct linux_pcic *pcic; |
|
/* struct linux_pbm_info* pbm = &pcic->pbm; */ |
|
int node; |
|
struct pcidev_cookie *pcp; |
|
|
|
if (!pcic0_up) { |
|
pci_info(bus, "pcibios_fixup_bus: no PCIC\n"); |
|
return; |
|
} |
|
pcic = &pcic0; |
|
|
|
/* |
|
* Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus); |
|
*/ |
|
if (bus->number != 0) { |
|
pci_info(bus, "pcibios_fixup_bus: nonzero bus 0x%x\n", |
|
bus->number); |
|
return; |
|
} |
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) { |
|
node = pdev_to_pnode(&pcic->pbm, dev); |
|
if(node == 0) |
|
node = -1; |
|
|
|
/* cookies */ |
|
pcp = pci_devcookie_alloc(); |
|
pcp->pbm = &pcic->pbm; |
|
pcp->prom_node = of_find_node_by_phandle(node); |
|
dev->sysdata = pcp; |
|
|
|
/* fixing I/O to look like memory */ |
|
if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE) |
|
pcic_map_pci_device(pcic, dev, node); |
|
|
|
pcic_fill_irq(pcic, dev, node); |
|
} |
|
} |
|
|
|
int pcibios_enable_device(struct pci_dev *dev, int mask) |
|
{ |
|
u16 cmd, oldcmd; |
|
int i; |
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd); |
|
oldcmd = cmd; |
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
|
struct resource *res = &dev->resource[i]; |
|
|
|
/* Only set up the requested stuff */ |
|
if (!(mask & (1<<i))) |
|
continue; |
|
|
|
if (res->flags & IORESOURCE_IO) |
|
cmd |= PCI_COMMAND_IO; |
|
if (res->flags & IORESOURCE_MEM) |
|
cmd |= PCI_COMMAND_MEMORY; |
|
} |
|
|
|
if (cmd != oldcmd) { |
|
pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd); |
|
pci_write_config_word(dev, PCI_COMMAND, cmd); |
|
} |
|
return 0; |
|
} |
|
|
|
/* Makes compiler happy */ |
|
static volatile int pcic_timer_dummy; |
|
|
|
static void pcic_clear_clock_irq(void) |
|
{ |
|
pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT); |
|
} |
|
|
|
/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */ |
|
#define USECS_PER_JIFFY (1000000 / HZ) |
|
#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ) |
|
|
|
static unsigned int pcic_cycles_offset(void) |
|
{ |
|
u32 value, count; |
|
|
|
value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER); |
|
count = value & ~PCI_SYS_COUNTER_OVERFLOW; |
|
|
|
if (value & PCI_SYS_COUNTER_OVERFLOW) |
|
count += TICK_TIMER_LIMIT; |
|
/* |
|
* We divide all by HZ |
|
* to have microsecond resolution and to avoid overflow |
|
*/ |
|
count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ); |
|
|
|
/* Coordinate with the sparc_config.clock_rate setting */ |
|
return count * 2; |
|
} |
|
|
|
void __init pci_time_init(void) |
|
{ |
|
struct linux_pcic *pcic = &pcic0; |
|
unsigned long v; |
|
int timer_irq, irq; |
|
int err; |
|
|
|
#ifndef CONFIG_SMP |
|
/* |
|
* The clock_rate is in SBUS dimension. |
|
* We take into account this in pcic_cycles_offset() |
|
*/ |
|
sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ; |
|
sparc_config.features |= FEAT_L10_CLOCKEVENT; |
|
#endif |
|
sparc_config.features |= FEAT_L10_CLOCKSOURCE; |
|
sparc_config.get_cycles_offset = pcic_cycles_offset; |
|
|
|
writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT); |
|
/* PROM should set appropriate irq */ |
|
v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ); |
|
timer_irq = PCI_COUNTER_IRQ_SYS(v); |
|
writel (PCI_COUNTER_IRQ_SET(timer_irq, 0), |
|
pcic->pcic_regs+PCI_COUNTER_IRQ); |
|
irq = pcic_build_device_irq(NULL, timer_irq); |
|
err = request_irq(irq, timer_interrupt, |
|
IRQF_TIMER, "timer", NULL); |
|
if (err) { |
|
prom_printf("time_init: unable to attach IRQ%d\n", timer_irq); |
|
prom_halt(); |
|
} |
|
local_irq_enable(); |
|
} |
|
|
|
|
|
#if 0 |
|
static void watchdog_reset() { |
|
writeb(0, pcic->pcic_regs+PCI_SYS_STATUS); |
|
} |
|
#endif |
|
|
|
/* |
|
* NMI |
|
*/ |
|
void pcic_nmi(unsigned int pend, struct pt_regs *regs) |
|
{ |
|
pend = swab32(pend); |
|
|
|
if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) { |
|
/* |
|
* XXX On CP-1200 PCI #SERR may happen, we do not know |
|
* what to do about it yet. |
|
*/ |
|
printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n", |
|
pend, (int)regs->pc, pcic_speculative); |
|
for (;;) { } |
|
} |
|
pcic_speculative = 0; |
|
pcic_trapped = 1; |
|
regs->pc = regs->npc; |
|
regs->npc += 4; |
|
} |
|
|
|
static inline unsigned long get_irqmask(int irq_nr) |
|
{ |
|
return 1 << irq_nr; |
|
} |
|
|
|
static void pcic_mask_irq(struct irq_data *data) |
|
{ |
|
unsigned long mask, flags; |
|
|
|
mask = (unsigned long)data->chip_data; |
|
local_irq_save(flags); |
|
writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); |
|
local_irq_restore(flags); |
|
} |
|
|
|
static void pcic_unmask_irq(struct irq_data *data) |
|
{ |
|
unsigned long mask, flags; |
|
|
|
mask = (unsigned long)data->chip_data; |
|
local_irq_save(flags); |
|
writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); |
|
local_irq_restore(flags); |
|
} |
|
|
|
static unsigned int pcic_startup_irq(struct irq_data *data) |
|
{ |
|
irq_link(data->irq); |
|
pcic_unmask_irq(data); |
|
return 0; |
|
} |
|
|
|
static struct irq_chip pcic_irq = { |
|
.name = "pcic", |
|
.irq_startup = pcic_startup_irq, |
|
.irq_mask = pcic_mask_irq, |
|
.irq_unmask = pcic_unmask_irq, |
|
}; |
|
|
|
unsigned int pcic_build_device_irq(struct platform_device *op, |
|
unsigned int real_irq) |
|
{ |
|
unsigned int irq; |
|
unsigned long mask; |
|
|
|
irq = 0; |
|
mask = get_irqmask(real_irq); |
|
if (mask == 0) |
|
goto out; |
|
|
|
irq = irq_alloc(real_irq, real_irq); |
|
if (irq == 0) |
|
goto out; |
|
|
|
irq_set_chip_and_handler_name(irq, &pcic_irq, |
|
handle_level_irq, "PCIC"); |
|
irq_set_chip_data(irq, (void *)mask); |
|
|
|
out: |
|
return irq; |
|
} |
|
|
|
|
|
static void pcic_load_profile_irq(int cpu, unsigned int limit) |
|
{ |
|
printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__); |
|
} |
|
|
|
void __init sun4m_pci_init_IRQ(void) |
|
{ |
|
sparc_config.build_device_irq = pcic_build_device_irq; |
|
sparc_config.clear_clock_irq = pcic_clear_clock_irq; |
|
sparc_config.load_profile_irq = pcic_load_profile_irq; |
|
} |
|
|
|
subsys_initcall(pcic_init);
|
|
|