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618 lines
22 KiB
618 lines
22 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* pci_psycho.c: PSYCHO/U2P specific PCI controller support. |
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* |
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* Copyright (C) 1997, 1998, 1999, 2007 David S. Miller ([email protected]) |
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* Copyright (C) 1998, 1999 Eddie C. Dost ([email protected]) |
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* Copyright (C) 1999 Jakub Jelinek ([email protected]) |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/export.h> |
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#include <linux/slab.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_device.h> |
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#include <asm/iommu.h> |
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#include <asm/irq.h> |
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#include <asm/starfire.h> |
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#include <asm/prom.h> |
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#include <asm/upa.h> |
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#include "pci_impl.h" |
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#include "iommu_common.h" |
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#include "psycho_common.h" |
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#define DRIVER_NAME "psycho" |
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#define PFX DRIVER_NAME ": " |
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/* Misc. PSYCHO PCI controller register offsets and definitions. */ |
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#define PSYCHO_CONTROL 0x0010UL |
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#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ |
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#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */ |
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#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */ |
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#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */ |
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#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */ |
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#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */ |
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#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */ |
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#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */ |
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#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */ |
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#define PSYCHO_PCIA_CTRL 0x2000UL |
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#define PSYCHO_PCIB_CTRL 0x4000UL |
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#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */ |
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#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */ |
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#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */ |
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#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */ |
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#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */ |
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#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */ |
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#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */ |
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#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */ |
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#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */ |
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#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */ |
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#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ |
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#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ |
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/* PSYCHO error handling support. */ |
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/* Helper function of IOMMU error checking, which checks out |
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* the state of the streaming buffers. The IOMMU lock is |
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* held when this is called. |
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* |
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* For the PCI error case we know which PBM (and thus which |
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* streaming buffer) caused the error, but for the uncorrectable |
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* error case we do not. So we always check both streaming caches. |
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*/ |
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#define PSYCHO_STRBUF_CONTROL_A 0x2800UL |
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#define PSYCHO_STRBUF_CONTROL_B 0x4800UL |
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#define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ |
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#define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ |
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#define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ |
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#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ |
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#define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ |
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#define PSYCHO_STRBUF_FLUSH_A 0x2808UL |
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#define PSYCHO_STRBUF_FLUSH_B 0x4808UL |
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#define PSYCHO_STRBUF_FSYNC_A 0x2810UL |
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#define PSYCHO_STRBUF_FSYNC_B 0x4810UL |
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#define PSYCHO_STC_DATA_A 0xb000UL |
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#define PSYCHO_STC_DATA_B 0xc000UL |
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#define PSYCHO_STC_ERR_A 0xb400UL |
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#define PSYCHO_STC_ERR_B 0xc400UL |
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#define PSYCHO_STC_TAG_A 0xb800UL |
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#define PSYCHO_STC_TAG_B 0xc800UL |
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#define PSYCHO_STC_LINE_A 0xb900UL |
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#define PSYCHO_STC_LINE_B 0xc900UL |
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/* When an Uncorrectable Error or a PCI Error happens, we |
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* interrogate the IOMMU state to see if it is the cause. |
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*/ |
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#define PSYCHO_IOMMU_CONTROL 0x0200UL |
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#define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ |
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#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ |
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#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ |
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#define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ |
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#define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ |
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#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ |
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#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ |
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#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ |
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#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ |
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#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ |
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#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ |
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#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ |
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#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ |
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#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ |
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#define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ |
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#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ |
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#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ |
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#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ |
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#define PSYCHO_IOMMU_TSBBASE 0x0208UL |
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#define PSYCHO_IOMMU_FLUSH 0x0210UL |
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#define PSYCHO_IOMMU_TAG 0xa580UL |
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#define PSYCHO_IOMMU_DATA 0xa600UL |
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/* Uncorrectable Errors. Cause of the error and the address are |
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* recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors |
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* relating to UPA interface transactions. |
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*/ |
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#define PSYCHO_UE_AFSR 0x0030UL |
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#define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ |
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#define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ |
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#define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ |
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#define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
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#define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ |
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#define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ |
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#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
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#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
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#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */ |
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#define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ |
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#define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ |
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#define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ |
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#define PSYCHO_UE_AFAR 0x0038UL |
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static irqreturn_t psycho_ue_intr(int irq, void *dev_id) |
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{ |
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struct pci_pbm_info *pbm = dev_id; |
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unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR; |
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unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR; |
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unsigned long afsr, afar, error_bits; |
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int reported; |
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/* Latch uncorrectable error status. */ |
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afar = upa_readq(afar_reg); |
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afsr = upa_readq(afsr_reg); |
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/* Clear the primary/secondary error status bits. */ |
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error_bits = afsr & |
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(PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR | |
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PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); |
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if (!error_bits) |
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return IRQ_NONE; |
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upa_writeq(error_bits, afsr_reg); |
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/* Log the error. */ |
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printk("%s: Uncorrectable Error, primary error type[%s]\n", |
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pbm->name, |
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(((error_bits & PSYCHO_UEAFSR_PPIO) ? |
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"PIO" : |
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((error_bits & PSYCHO_UEAFSR_PDRD) ? |
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"DMA Read" : |
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((error_bits & PSYCHO_UEAFSR_PDWR) ? |
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"DMA Write" : "???"))))); |
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printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n", |
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pbm->name, |
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(afsr & PSYCHO_UEAFSR_BMSK) >> 32UL, |
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(afsr & PSYCHO_UEAFSR_DOFF) >> 29UL, |
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(afsr & PSYCHO_UEAFSR_MID) >> 24UL, |
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((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0)); |
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printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); |
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printk("%s: UE Secondary errors [", pbm->name); |
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reported = 0; |
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if (afsr & PSYCHO_UEAFSR_SPIO) { |
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reported++; |
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printk("(PIO)"); |
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} |
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if (afsr & PSYCHO_UEAFSR_SDRD) { |
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reported++; |
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printk("(DMA Read)"); |
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} |
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if (afsr & PSYCHO_UEAFSR_SDWR) { |
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reported++; |
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printk("(DMA Write)"); |
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} |
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if (!reported) |
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printk("(none)"); |
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printk("]\n"); |
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/* Interrogate both IOMMUs for error status. */ |
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psycho_check_iommu_error(pbm, afsr, afar, UE_ERR); |
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if (pbm->sibling) |
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psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR); |
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return IRQ_HANDLED; |
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} |
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/* Correctable Errors. */ |
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#define PSYCHO_CE_AFSR 0x0040UL |
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#define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ |
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#define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ |
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#define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ |
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#define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
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#define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ |
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#define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ |
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#define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ |
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#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ |
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#define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
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#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */ |
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#define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ |
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#define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ |
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#define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ |
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#define PSYCHO_CE_AFAR 0x0040UL |
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static irqreturn_t psycho_ce_intr(int irq, void *dev_id) |
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{ |
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struct pci_pbm_info *pbm = dev_id; |
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unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR; |
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unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR; |
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unsigned long afsr, afar, error_bits; |
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int reported; |
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/* Latch error status. */ |
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afar = upa_readq(afar_reg); |
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afsr = upa_readq(afsr_reg); |
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/* Clear primary/secondary error status bits. */ |
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error_bits = afsr & |
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(PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR | |
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PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); |
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if (!error_bits) |
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return IRQ_NONE; |
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upa_writeq(error_bits, afsr_reg); |
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/* Log the error. */ |
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printk("%s: Correctable Error, primary error type[%s]\n", |
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pbm->name, |
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(((error_bits & PSYCHO_CEAFSR_PPIO) ? |
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"PIO" : |
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((error_bits & PSYCHO_CEAFSR_PDRD) ? |
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"DMA Read" : |
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((error_bits & PSYCHO_CEAFSR_PDWR) ? |
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"DMA Write" : "???"))))); |
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/* XXX Use syndrome and afar to print out module string just like |
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* XXX UDB CE trap handler does... -DaveM |
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*/ |
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printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
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"UPA_MID[%02lx] was_block(%d)\n", |
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pbm->name, |
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(afsr & PSYCHO_CEAFSR_ESYND) >> 48UL, |
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(afsr & PSYCHO_CEAFSR_BMSK) >> 32UL, |
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(afsr & PSYCHO_CEAFSR_DOFF) >> 29UL, |
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(afsr & PSYCHO_CEAFSR_MID) >> 24UL, |
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((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0)); |
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printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); |
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printk("%s: CE Secondary errors [", pbm->name); |
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reported = 0; |
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if (afsr & PSYCHO_CEAFSR_SPIO) { |
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reported++; |
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printk("(PIO)"); |
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} |
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if (afsr & PSYCHO_CEAFSR_SDRD) { |
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reported++; |
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printk("(DMA Read)"); |
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} |
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if (afsr & PSYCHO_CEAFSR_SDWR) { |
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reported++; |
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printk("(DMA Write)"); |
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} |
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if (!reported) |
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printk("(none)"); |
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printk("]\n"); |
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return IRQ_HANDLED; |
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} |
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/* PCI Errors. They are signalled by the PCI bus module since they |
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* are associated with a specific bus segment. |
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*/ |
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#define PSYCHO_PCI_AFSR_A 0x2010UL |
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#define PSYCHO_PCI_AFSR_B 0x4010UL |
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#define PSYCHO_PCI_AFAR_A 0x2018UL |
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#define PSYCHO_PCI_AFAR_B 0x4018UL |
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/* XXX What about PowerFail/PowerManagement??? -DaveM */ |
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#define PSYCHO_ECC_CTRL 0x0020 |
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#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ |
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#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ |
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#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ |
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static void psycho_register_error_handlers(struct pci_pbm_info *pbm) |
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{ |
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struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); |
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unsigned long base = pbm->controller_regs; |
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u64 tmp; |
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int err; |
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if (!op) |
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return; |
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/* Psycho interrupt property order is: |
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* 0: PCIERR INO for this PBM |
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* 1: UE ERR |
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* 2: CE ERR |
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* 3: POWER FAIL |
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* 4: SPARE HARDWARE |
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* 5: POWER MANAGEMENT |
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*/ |
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if (op->archdata.num_irqs < 6) |
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return; |
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/* We really mean to ignore the return result here. Two |
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* PCI controller share the same interrupt numbers and |
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* drive the same front-end hardware. |
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*/ |
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err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED, |
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"PSYCHO_UE", pbm); |
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err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED, |
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"PSYCHO_CE", pbm); |
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/* This one, however, ought not to fail. We can just warn |
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* about it since the system can still operate properly even |
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* if this fails. |
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*/ |
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err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED, |
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"PSYCHO_PCIERR", pbm); |
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if (err) |
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printk(KERN_WARNING "%s: Could not register PCIERR, " |
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"err=%d\n", pbm->name, err); |
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/* Enable UE and CE interrupts for controller. */ |
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upa_writeq((PSYCHO_ECCCTRL_EE | |
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PSYCHO_ECCCTRL_UE | |
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PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL); |
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/* Enable PCI Error interrupts and clear error |
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* bits for each PBM. |
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*/ |
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tmp = upa_readq(base + PSYCHO_PCIA_CTRL); |
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tmp |= (PSYCHO_PCICTRL_SERR | |
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PSYCHO_PCICTRL_SBH_ERR | |
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PSYCHO_PCICTRL_EEN); |
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tmp &= ~(PSYCHO_PCICTRL_SBH_INT); |
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upa_writeq(tmp, base + PSYCHO_PCIA_CTRL); |
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tmp = upa_readq(base + PSYCHO_PCIB_CTRL); |
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tmp |= (PSYCHO_PCICTRL_SERR | |
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PSYCHO_PCICTRL_SBH_ERR | |
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PSYCHO_PCICTRL_EEN); |
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tmp &= ~(PSYCHO_PCICTRL_SBH_INT); |
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upa_writeq(tmp, base + PSYCHO_PCIB_CTRL); |
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} |
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/* PSYCHO boot time probing and initialization. */ |
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static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
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{ |
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u8 *addr; |
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/* Set cache-line size to 64 bytes, this is actually |
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* a nop but I do it for completeness. |
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*/ |
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addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
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0, PCI_CACHE_LINE_SIZE); |
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pci_config_write8(addr, 64 / sizeof(u32)); |
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/* Set PBM latency timer to 64 PCI clocks. */ |
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addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
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0, PCI_LATENCY_TIMER); |
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pci_config_write8(addr, 64); |
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} |
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static void psycho_scan_bus(struct pci_pbm_info *pbm, |
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struct device *parent) |
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{ |
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pbm_config_busmastering(pbm); |
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pbm->is_66mhz_capable = 0; |
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pbm->pci_bus = pci_scan_one_pbm(pbm, parent); |
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|
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/* After the PCI bus scan is complete, we can register |
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* the error interrupt handlers. |
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*/ |
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psycho_register_error_handlers(pbm); |
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} |
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#define PSYCHO_IRQ_RETRY 0x1a00UL |
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#define PSYCHO_PCIA_DIAG 0x2020UL |
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#define PSYCHO_PCIB_DIAG 0x4020UL |
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#define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */ |
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#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */ |
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#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */ |
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#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */ |
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#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */ |
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#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */ |
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#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ |
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#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ |
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|
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static void psycho_controller_hwinit(struct pci_pbm_info *pbm) |
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{ |
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u64 tmp; |
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upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY); |
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|
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/* Enable arbiter for all PCI slots. */ |
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tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL); |
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tmp |= PSYCHO_PCICTRL_AEN; |
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upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL); |
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tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL); |
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tmp |= PSYCHO_PCICTRL_AEN; |
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upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL); |
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|
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/* Disable DMA write / PIO read synchronization on |
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* both PCI bus segments. |
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* [ U2P Erratum 1243770, STP2223BGA data sheet ] |
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*/ |
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tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG); |
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tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
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upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG); |
|
|
|
tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG); |
|
tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
|
upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG); |
|
} |
|
|
|
static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, |
|
int is_pbm_a) |
|
{ |
|
unsigned long base = pbm->controller_regs; |
|
u64 control; |
|
|
|
if (is_pbm_a) { |
|
pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; |
|
pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; |
|
pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; |
|
pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A; |
|
pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A; |
|
pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A; |
|
} else { |
|
pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; |
|
pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; |
|
pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; |
|
pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B; |
|
pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B; |
|
pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B; |
|
} |
|
/* PSYCHO's streaming buffer lacks ctx flushing. */ |
|
pbm->stc.strbuf_ctxflush = 0; |
|
pbm->stc.strbuf_ctxmatch_base = 0; |
|
|
|
pbm->stc.strbuf_flushflag = (volatile unsigned long *) |
|
((((unsigned long)&pbm->stc.__flushflag_buf[0]) |
|
+ 63UL) |
|
& ~63UL); |
|
pbm->stc.strbuf_flushflag_pa = (unsigned long) |
|
__pa(pbm->stc.strbuf_flushflag); |
|
|
|
/* Enable the streaming buffer. We have to be careful |
|
* just in case OBP left it with LRU locking enabled. |
|
* |
|
* It is possible to control if PBM will be rerun on |
|
* line misses. Currently I just retain whatever setting |
|
* OBP left us with. All checks so far show it having |
|
* a value of zero. |
|
*/ |
|
#undef PSYCHO_STRBUF_RERUN_ENABLE |
|
#undef PSYCHO_STRBUF_RERUN_DISABLE |
|
control = upa_readq(pbm->stc.strbuf_control); |
|
control |= PSYCHO_STRBUF_CTRL_ENAB; |
|
control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); |
|
#ifdef PSYCHO_STRBUF_RERUN_ENABLE |
|
control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); |
|
#else |
|
#ifdef PSYCHO_STRBUF_RERUN_DISABLE |
|
control |= PSYCHO_STRBUF_CTRL_RRDIS; |
|
#endif |
|
#endif |
|
upa_writeq(control, pbm->stc.strbuf_control); |
|
|
|
pbm->stc.strbuf_enabled = 1; |
|
} |
|
|
|
#define PSYCHO_IOSPACE_A 0x002000000UL |
|
#define PSYCHO_IOSPACE_B 0x002010000UL |
|
#define PSYCHO_IOSPACE_SIZE 0x00000ffffUL |
|
#define PSYCHO_MEMSPACE_A 0x100000000UL |
|
#define PSYCHO_MEMSPACE_B 0x180000000UL |
|
#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL |
|
|
|
static void psycho_pbm_init(struct pci_pbm_info *pbm, |
|
struct platform_device *op, int is_pbm_a) |
|
{ |
|
psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO); |
|
psycho_pbm_strbuf_init(pbm, is_pbm_a); |
|
psycho_scan_bus(pbm, &op->dev); |
|
} |
|
|
|
static struct pci_pbm_info *psycho_find_sibling(u32 upa_portid) |
|
{ |
|
struct pci_pbm_info *pbm; |
|
|
|
for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { |
|
if (pbm->portid == upa_portid) |
|
return pbm; |
|
} |
|
return NULL; |
|
} |
|
|
|
#define PSYCHO_CONFIGSPACE 0x001000000UL |
|
|
|
static int psycho_probe(struct platform_device *op) |
|
{ |
|
const struct linux_prom64_registers *pr_regs; |
|
struct device_node *dp = op->dev.of_node; |
|
struct pci_pbm_info *pbm; |
|
struct iommu *iommu; |
|
int is_pbm_a, err; |
|
u32 upa_portid; |
|
|
|
upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); |
|
|
|
err = -ENOMEM; |
|
pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); |
|
if (!pbm) { |
|
printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); |
|
goto out_err; |
|
} |
|
|
|
pbm->sibling = psycho_find_sibling(upa_portid); |
|
if (pbm->sibling) { |
|
iommu = pbm->sibling->iommu; |
|
} else { |
|
iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); |
|
if (!iommu) { |
|
printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); |
|
goto out_free_controller; |
|
} |
|
} |
|
|
|
pbm->iommu = iommu; |
|
pbm->portid = upa_portid; |
|
|
|
pr_regs = of_get_property(dp, "reg", NULL); |
|
err = -ENODEV; |
|
if (!pr_regs) { |
|
printk(KERN_ERR PFX "No reg property.\n"); |
|
goto out_free_iommu; |
|
} |
|
|
|
is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); |
|
|
|
pbm->controller_regs = pr_regs[2].phys_addr; |
|
pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); |
|
|
|
if (is_pbm_a) { |
|
pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A; |
|
pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A; |
|
pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL; |
|
} else { |
|
pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B; |
|
pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B; |
|
pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL; |
|
} |
|
|
|
psycho_controller_hwinit(pbm); |
|
if (!pbm->sibling) { |
|
err = psycho_iommu_init(pbm, 128, 0xc0000000, |
|
0xffffffff, PSYCHO_CONTROL); |
|
if (err) |
|
goto out_free_iommu; |
|
|
|
/* If necessary, hook us up for starfire IRQ translations. */ |
|
if (this_is_starfire) |
|
starfire_hookup(pbm->portid); |
|
} |
|
|
|
psycho_pbm_init(pbm, op, is_pbm_a); |
|
|
|
pbm->next = pci_pbm_root; |
|
pci_pbm_root = pbm; |
|
|
|
if (pbm->sibling) |
|
pbm->sibling->sibling = pbm; |
|
|
|
dev_set_drvdata(&op->dev, pbm); |
|
|
|
return 0; |
|
|
|
out_free_iommu: |
|
if (!pbm->sibling) |
|
kfree(pbm->iommu); |
|
|
|
out_free_controller: |
|
kfree(pbm); |
|
|
|
out_err: |
|
return err; |
|
} |
|
|
|
static const struct of_device_id psycho_match[] = { |
|
{ |
|
.name = "pci", |
|
.compatible = "pci108e,8000", |
|
}, |
|
{}, |
|
}; |
|
|
|
static struct platform_driver psycho_driver = { |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.of_match_table = psycho_match, |
|
}, |
|
.probe = psycho_probe, |
|
}; |
|
|
|
static int __init psycho_init(void) |
|
{ |
|
return platform_driver_register(&psycho_driver); |
|
} |
|
|
|
subsys_initcall(psycho_init);
|
|
|