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270 lines
5.8 KiB
270 lines
5.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling. |
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* |
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* Copyright (C) 1995, 1997, 2005, 2008 David S. Miller <davem@davemloft.net> |
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* Copyright (C) 1996 Eddie C. Dost (ecd@brainaid.de) |
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* Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) |
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* Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
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*/ |
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#include <linux/pgtable.h> |
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#include <asm/head.h> |
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#include <asm/asi.h> |
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#include <asm/page.h> |
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#include <asm/tsb.h> |
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.text |
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.align 32 |
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kvmap_itlb: |
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/* g6: TAG TARGET */ |
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mov TLB_TAG_ACCESS, %g4 |
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ldxa [%g4] ASI_IMMU, %g4 |
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/* The kernel executes in context zero, therefore we do not |
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* need to clear the context ID bits out of %g4 here. |
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*/ |
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/* sun4v_itlb_miss branches here with the missing virtual |
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* address already loaded into %g4 |
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*/ |
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kvmap_itlb_4v: |
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/* Catch kernel NULL pointer calls. */ |
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sethi %hi(PAGE_SIZE), %g5 |
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cmp %g4, %g5 |
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blu,pn %xcc, kvmap_itlb_longpath |
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nop |
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KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load) |
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kvmap_itlb_tsb_miss: |
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sethi %hi(LOW_OBP_ADDRESS), %g5 |
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cmp %g4, %g5 |
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blu,pn %xcc, kvmap_itlb_vmalloc_addr |
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mov 0x1, %g5 |
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sllx %g5, 32, %g5 |
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cmp %g4, %g5 |
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blu,pn %xcc, kvmap_itlb_obp |
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nop |
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kvmap_itlb_vmalloc_addr: |
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath) |
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TSB_LOCK_TAG(%g1, %g2, %g7) |
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TSB_WRITE(%g1, %g5, %g6) |
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/* fallthrough to TLB load */ |
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kvmap_itlb_load: |
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661: stxa %g5, [%g0] ASI_ITLB_DATA_IN |
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retry |
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.section .sun4v_2insn_patch, "ax" |
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.word 661b |
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nop |
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nop |
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.previous |
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/* For sun4v the ASI_ITLB_DATA_IN store and the retry |
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* instruction get nop'd out and we get here to branch |
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* to the sun4v tlb load code. The registers are setup |
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* as follows: |
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* |
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* %g4: vaddr |
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* %g5: PTE |
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* %g6: TAG |
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* |
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* The sun4v TLB load wants the PTE in %g3 so we fix that |
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* up here. |
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*/ |
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ba,pt %xcc, sun4v_itlb_load |
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mov %g5, %g3 |
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kvmap_itlb_longpath: |
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661: rdpr %pstate, %g5 |
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate |
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.section .sun4v_2insn_patch, "ax" |
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.word 661b |
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SET_GL(1) |
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nop |
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.previous |
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rdpr %tpc, %g5 |
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ba,pt %xcc, sparc64_realfault_common |
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mov FAULT_CODE_ITLB, %g4 |
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kvmap_itlb_obp: |
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath) |
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TSB_LOCK_TAG(%g1, %g2, %g7) |
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TSB_WRITE(%g1, %g5, %g6) |
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ba,pt %xcc, kvmap_itlb_load |
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nop |
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kvmap_dtlb_obp: |
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath) |
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TSB_LOCK_TAG(%g1, %g2, %g7) |
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TSB_WRITE(%g1, %g5, %g6) |
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ba,pt %xcc, kvmap_dtlb_load |
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nop |
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kvmap_linear_early: |
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sethi %hi(kern_linear_pte_xor), %g7 |
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ldx [%g7 + %lo(kern_linear_pte_xor)], %g2 |
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ba,pt %xcc, kvmap_dtlb_tsb4m_load |
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xor %g2, %g4, %g5 |
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.align 32 |
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kvmap_dtlb_tsb4m_load: |
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TSB_LOCK_TAG(%g1, %g2, %g7) |
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TSB_WRITE(%g1, %g5, %g6) |
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ba,pt %xcc, kvmap_dtlb_load |
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nop |
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kvmap_dtlb: |
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/* %g6: TAG TARGET */ |
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mov TLB_TAG_ACCESS, %g4 |
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ldxa [%g4] ASI_DMMU, %g4 |
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/* The kernel executes in context zero, therefore we do not |
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* need to clear the context ID bits out of %g4 here. |
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*/ |
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/* sun4v_dtlb_miss branches here with the missing virtual |
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* address already loaded into %g4 |
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*/ |
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kvmap_dtlb_4v: |
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brgez,pn %g4, kvmap_dtlb_nonlinear |
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nop |
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#ifdef CONFIG_DEBUG_PAGEALLOC |
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/* Index through the base page size TSB even for linear |
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* mappings when using page allocation debugging. |
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*/ |
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KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load) |
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#else |
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/* Correct TAG_TARGET is already in %g6, check 4mb TSB. */ |
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KERN_TSB4M_LOOKUP_TL1(%g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load) |
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#endif |
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/* Linear mapping TSB lookup failed. Fallthrough to kernel |
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* page table based lookup. |
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*/ |
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.globl kvmap_linear_patch |
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kvmap_linear_patch: |
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ba,a,pt %xcc, kvmap_linear_early |
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kvmap_dtlb_vmalloc_addr: |
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath) |
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TSB_LOCK_TAG(%g1, %g2, %g7) |
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TSB_WRITE(%g1, %g5, %g6) |
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/* fallthrough to TLB load */ |
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kvmap_dtlb_load: |
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661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB |
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retry |
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.section .sun4v_2insn_patch, "ax" |
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.word 661b |
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nop |
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nop |
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.previous |
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/* For sun4v the ASI_DTLB_DATA_IN store and the retry |
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* instruction get nop'd out and we get here to branch |
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* to the sun4v tlb load code. The registers are setup |
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* as follows: |
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* |
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* %g4: vaddr |
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* %g5: PTE |
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* %g6: TAG |
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* |
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* The sun4v TLB load wants the PTE in %g3 so we fix that |
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* up here. |
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*/ |
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ba,pt %xcc, sun4v_dtlb_load |
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mov %g5, %g3 |
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#ifdef CONFIG_SPARSEMEM_VMEMMAP |
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kvmap_vmemmap: |
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath) |
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ba,a,pt %xcc, kvmap_dtlb_load |
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#endif |
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kvmap_dtlb_nonlinear: |
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/* Catch kernel NULL pointer derefs. */ |
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sethi %hi(PAGE_SIZE), %g5 |
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cmp %g4, %g5 |
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bleu,pn %xcc, kvmap_dtlb_longpath |
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nop |
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#ifdef CONFIG_SPARSEMEM_VMEMMAP |
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/* Do not use the TSB for vmemmap. */ |
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sethi %hi(VMEMMAP_BASE), %g5 |
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ldx [%g5 + %lo(VMEMMAP_BASE)], %g5 |
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cmp %g4,%g5 |
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bgeu,pn %xcc, kvmap_vmemmap |
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nop |
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#endif |
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KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load) |
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kvmap_dtlb_tsbmiss: |
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sethi %hi(MODULES_VADDR), %g5 |
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cmp %g4, %g5 |
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blu,pn %xcc, kvmap_dtlb_longpath |
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sethi %hi(VMALLOC_END), %g5 |
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ldx [%g5 + %lo(VMALLOC_END)], %g5 |
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cmp %g4, %g5 |
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bgeu,pn %xcc, kvmap_dtlb_longpath |
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nop |
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kvmap_check_obp: |
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sethi %hi(LOW_OBP_ADDRESS), %g5 |
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cmp %g4, %g5 |
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blu,pn %xcc, kvmap_dtlb_vmalloc_addr |
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mov 0x1, %g5 |
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sllx %g5, 32, %g5 |
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cmp %g4, %g5 |
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blu,pn %xcc, kvmap_dtlb_obp |
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nop |
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ba,pt %xcc, kvmap_dtlb_vmalloc_addr |
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nop |
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kvmap_dtlb_longpath: |
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661: rdpr %pstate, %g5 |
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate |
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.section .sun4v_2insn_patch, "ax" |
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.word 661b |
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SET_GL(1) |
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ldxa [%g0] ASI_SCRATCHPAD, %g5 |
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.previous |
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rdpr %tl, %g3 |
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cmp %g3, 1 |
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661: mov TLB_TAG_ACCESS, %g4 |
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ldxa [%g4] ASI_DMMU, %g5 |
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.section .sun4v_2insn_patch, "ax" |
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.word 661b |
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ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5 |
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nop |
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.previous |
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/* The kernel executes in context zero, therefore we do not |
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* need to clear the context ID bits out of %g5 here. |
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*/ |
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be,pt %xcc, sparc64_realfault_common |
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mov FAULT_CODE_DTLB, %g4 |
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ba,pt %xcc, winfix_trampoline |
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nop
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