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812 lines
19 KiB
812 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* head.S: The initial boot code for the Sparc port of Linux. |
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* |
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) |
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* Copyright (C) 1995,1999 Pete Zaitcev (zaitcev@yahoo.com) |
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* Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) |
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* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
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* Copyright (C) 1997 Michael A. Griffith (grif@acm.org) |
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* |
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* CompactPCI platform by Eric Brower, 1999. |
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*/ |
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#include <linux/version.h> |
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#include <linux/init.h> |
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|
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#include <asm/head.h> |
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#include <asm/asi.h> |
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#include <asm/contregs.h> |
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#include <asm/ptrace.h> |
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#include <asm/psr.h> |
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#include <asm/page.h> |
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#include <asm/kdebug.h> |
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#include <asm/winmacro.h> |
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#include <asm/thread_info.h> /* TI_UWINMASK */ |
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#include <asm/errno.h> |
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#include <asm/pgtable.h> /* PGDIR_SHIFT */ |
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#include <asm/export.h> |
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.data |
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/* The following are used with the prom_vector node-ops to figure out |
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* the cpu-type |
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*/ |
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.align 4 |
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.globl cputypval |
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cputypval: |
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.asciz "sun4m" |
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.ascii " " |
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|
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/* Tested on SS-5, SS-10 */ |
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.align 4 |
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cputypvar: |
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.asciz "compatible" |
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.align 4 |
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notsup: |
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.asciz "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n" |
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.align 4 |
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sun4e_notsup: |
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.asciz "Sparc-Linux sun4e support does not exist\n\n" |
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.align 4 |
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/* The trap-table - located in the __HEAD section */ |
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#include "ttable_32.S" |
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.align PAGE_SIZE |
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/* This was the only reasonable way I could think of to properly align |
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* these page-table data structures. |
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*/ |
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.globl empty_zero_page |
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empty_zero_page: .skip PAGE_SIZE |
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EXPORT_SYMBOL(empty_zero_page) |
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.global root_flags |
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.global ram_flags |
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.global root_dev |
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.global sparc_ramdisk_image |
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.global sparc_ramdisk_size |
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/* This stuff has to be in sync with SILO and other potential boot loaders |
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* Fields should be kept upward compatible and whenever any change is made, |
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* HdrS version should be incremented. |
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*/ |
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.ascii "HdrS" |
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.word LINUX_VERSION_CODE |
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.half 0x0203 /* HdrS version */ |
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root_flags: |
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.half 1 |
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root_dev: |
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.half 0 |
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ram_flags: |
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.half 0 |
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sparc_ramdisk_image: |
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.word 0 |
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sparc_ramdisk_size: |
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.word 0 |
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.word reboot_command |
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.word 0, 0, 0 |
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.word _end |
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/* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in |
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* %g7 and at prom_vector_p. And also quickly check whether we are on |
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* a v0, v2, or v3 prom. |
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*/ |
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gokernel: |
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/* Ok, it's nice to know, as early as possible, if we |
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* are already mapped where we expect to be in virtual |
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* memory. The Solaris /boot elf format bootloader |
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* will peek into our elf header and load us where |
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* we want to be, otherwise we have to re-map. |
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* |
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* Some boot loaders don't place the jmp'rs address |
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* in %o7, so we do a pc-relative call to a local |
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* label, then see what %o7 has. |
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*/ |
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mov %o7, %g4 ! Save %o7 |
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/* Jump to it, and pray... */ |
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current_pc: |
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call 1f |
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nop |
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1: |
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mov %o7, %g3 |
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tst %o0 |
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be no_sun4u_here |
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mov %g4, %o7 /* Previous %o7. */ |
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mov %o0, %l0 ! stash away romvec |
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mov %o0, %g7 ! put it here too |
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mov %o1, %l1 ! stash away debug_vec too |
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/* Ok, let's check out our run time program counter. */ |
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set current_pc, %g5 |
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cmp %g3, %g5 |
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be already_mapped |
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nop |
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/* %l6 will hold the offset we have to subtract |
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* from absolute symbols in order to access areas |
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* in our own image. If already mapped this is |
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* just plain zero, else it is KERNBASE. |
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*/ |
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set KERNBASE, %l6 |
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b copy_prom_lvl14 |
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nop |
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already_mapped: |
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mov 0, %l6 |
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/* Copy over the Prom's level 14 clock handler. */ |
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copy_prom_lvl14: |
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#if 1 |
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/* DJHR |
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* preserve our linked/calculated instructions |
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*/ |
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set lvl14_save, %g1 |
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set t_irq14, %g3 |
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sub %g1, %l6, %g1 ! translate to physical |
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sub %g3, %l6, %g3 ! translate to physical |
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ldd [%g3], %g4 |
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std %g4, [%g1] |
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ldd [%g3+8], %g4 |
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std %g4, [%g1+8] |
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#endif |
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rd %tbr, %g1 |
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andn %g1, 0xfff, %g1 ! proms trap table base |
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or %g0, (0x1e<<4), %g2 ! offset to lvl14 intr |
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or %g1, %g2, %g2 |
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set t_irq14, %g3 |
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sub %g3, %l6, %g3 |
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ldd [%g2], %g4 |
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std %g4, [%g3] |
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ldd [%g2 + 0x8], %g4 |
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std %g4, [%g3 + 0x8] ! Copy proms handler |
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/* DON'T TOUCH %l0 thru %l5 in these remapping routines, |
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* we need their values afterwards! |
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*/ |
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/* Now check whether we are already mapped, if we |
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* are we can skip all this garbage coming up. |
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*/ |
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copy_prom_done: |
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cmp %l6, 0 |
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be go_to_highmem ! this will be a nop then |
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nop |
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/* Validate that we are in fact running on an |
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* SRMMU based cpu. |
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*/ |
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set 0x4000, %g6 |
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cmp %g7, %g6 |
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bne not_a_sun4 |
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nop |
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halt_notsup: |
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ld [%g7 + 0x68], %o1 |
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set notsup, %o0 |
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sub %o0, %l6, %o0 |
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call %o1 |
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nop |
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ba halt_me |
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nop |
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not_a_sun4: |
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/* It looks like this is a machine we support. |
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* Now find out what MMU we are dealing with |
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* LEON - identified by the psr.impl field |
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* Viking - identified by the psr.impl field |
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* In all other cases a sun4m srmmu. |
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* We check that the MMU is enabled in all cases. |
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*/ |
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/* Check if this is a LEON CPU */ |
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rd %psr, %g3 |
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srl %g3, PSR_IMPL_SHIFT, %g3 |
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and %g3, PSR_IMPL_SHIFTED_MASK, %g3 |
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cmp %g3, PSR_IMPL_LEON |
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be leon_remap /* It is a LEON - jump */ |
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nop |
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/* Sanity-check, is MMU enabled */ |
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lda [%g0] ASI_M_MMUREGS, %g1 |
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andcc %g1, 1, %g0 |
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be halt_notsup |
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nop |
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/* Check for a viking (TI) module. */ |
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cmp %g3, PSR_IMPL_TI |
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bne srmmu_not_viking |
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nop |
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/* Figure out what kind of viking we are on. |
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* We need to know if we have to play with the |
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* AC bit and disable traps or not. |
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*/ |
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/* I've only seen MicroSparc's on SparcClassics with this |
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* bit set. |
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*/ |
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set 0x800, %g2 |
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lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg |
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and %g2, %g3, %g3 |
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subcc %g3, 0x0, %g0 |
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bnz srmmu_not_viking ! is in mbus mode |
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nop |
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rd %psr, %g3 ! DO NOT TOUCH %g3 |
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andn %g3, PSR_ET, %g2 |
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wr %g2, 0x0, %psr |
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WRITE_PAUSE |
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/* Get context table pointer, then convert to |
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* a physical address, which is 36 bits. |
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*/ |
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set AC_M_CTPR, %g4 |
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lda [%g4] ASI_M_MMUREGS, %g4 |
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sll %g4, 0x4, %g4 ! We use this below |
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! DO NOT TOUCH %g4 |
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/* Set the AC bit in the Viking's MMU control reg. */ |
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lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5 |
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set 0x8000, %g6 ! AC bit mask |
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or %g5, %g6, %g6 ! Or it in... |
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sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes... |
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/* Grrr, why does it seem like every other load/store |
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* on the sun4m is in some ASI space... |
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* Fine with me, let's get the pointer to the level 1 |
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* page table directory and fetch its entry. |
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*/ |
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lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr |
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srl %o1, 0x4, %o1 ! Clear low 4 bits |
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sll %o1, 0x8, %o1 ! Make physical |
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/* Ok, pull in the PTD. */ |
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lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd |
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/* Calculate to KERNBASE entry. */ |
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add %o1, KERNBASE >> (PGDIR_SHIFT - 2), %o3 |
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/* Poke the entry into the calculated address. */ |
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sta %o2, [%o3] ASI_M_BYPASS |
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/* I don't get it Sun, if you engineered all these |
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* boot loaders and the PROM (thank you for the debugging |
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* features btw) why did you not have them load kernel |
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* images up in high address space, since this is necessary |
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* for ABI compliance anyways? Does this low-mapping provide |
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* enhanced interoperability? |
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* |
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* "The PROM is the computer." |
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*/ |
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/* Ok, restore the MMU control register we saved in %g5 */ |
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sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch |
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/* Turn traps back on. We saved it in %g3 earlier. */ |
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wr %g3, 0x0, %psr ! tick tock, tick tock |
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/* Now we burn precious CPU cycles due to bad engineering. */ |
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WRITE_PAUSE |
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/* Wow, all that just to move a 32-bit value from one |
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* place to another... Jump to high memory. |
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*/ |
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b go_to_highmem |
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nop |
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srmmu_not_viking: |
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/* This works on viking's in Mbus mode and all |
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* other MBUS modules. It is virtually the same as |
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* the above madness sans turning traps off and flipping |
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* the AC bit. |
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*/ |
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set AC_M_CTPR, %g1 |
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lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr |
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sll %g1, 0x4, %g1 ! make physical addr |
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lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table |
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srl %g1, 0x4, %g1 |
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sll %g1, 0x8, %g1 ! make phys addr for l1 tbl |
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lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 |
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add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3 |
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sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry |
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b go_to_highmem |
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nop ! wheee.... |
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leon_remap: |
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/* Sanity-check, is MMU enabled */ |
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lda [%g0] ASI_LEON_MMUREGS, %g1 |
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andcc %g1, 1, %g0 |
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be halt_notsup |
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nop |
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/* Same code as in the srmmu_not_viking case, |
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* with the LEON ASI for mmuregs |
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*/ |
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set AC_M_CTPR, %g1 |
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lda [%g1] ASI_LEON_MMUREGS, %g1 ! get ctx table ptr |
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sll %g1, 0x4, %g1 ! make physical addr |
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lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table |
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srl %g1, 0x4, %g1 |
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sll %g1, 0x8, %g1 ! make phys addr for l1 tbl |
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lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 |
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add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3 |
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sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry |
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b go_to_highmem |
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nop ! wheee.... |
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/* Now do a non-relative jump so that PC is in high-memory */ |
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go_to_highmem: |
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set execute_in_high_mem, %g1 |
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jmpl %g1, %g0 |
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nop |
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/* The code above should be at beginning and we have to take care about |
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* short jumps, as branching to .init.text section from .text is usually |
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* impossible */ |
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__INIT |
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/* Acquire boot time privileged register values, this will help debugging. |
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* I figure out and store nwindows and nwindowsm1 later on. |
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*/ |
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execute_in_high_mem: |
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mov %l0, %o0 ! put back romvec |
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mov %l1, %o1 ! and debug_vec |
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sethi %hi(prom_vector_p), %g1 |
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st %o0, [%g1 + %lo(prom_vector_p)] |
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sethi %hi(linux_dbvec), %g1 |
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st %o1, [%g1 + %lo(linux_dbvec)] |
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/* Get the machine type via the romvec |
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* getprops node operation |
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*/ |
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add %g7, 0x1c, %l1 |
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ld [%l1], %l0 |
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ld [%l0], %l0 |
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call %l0 |
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or %g0, %g0, %o0 ! next_node(0) = first_node |
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or %o0, %g0, %g6 |
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sethi %hi(cputypvar), %o1 ! First node has cpu-arch |
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or %o1, %lo(cputypvar), %o1 |
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sethi %hi(cputypval), %o2 ! information, the string |
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or %o2, %lo(cputypval), %o2 |
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ld [%l1], %l0 ! 'compatible' tells |
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ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where |
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call %l0 ! x is one of 'm', 'd' or 'e'. |
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nop ! %o2 holds pointer |
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! to a buf where above string |
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! will get stored by the prom. |
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/* Check value of "compatible" property. |
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* "value" => "model" |
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* leon => sparc_leon |
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* sun4m => sun4m |
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* sun4s => sun4m |
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* sun4d => sun4d |
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* sun4e => "no_sun4e_here" |
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* '*' => "no_sun4u_here" |
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* Check single letters only |
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*/ |
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set cputypval, %o2 |
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/* If cputypval[0] == 'l' (lower case letter L) this is leon */ |
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ldub [%o2], %l1 |
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cmp %l1, 'l' |
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be leon_init |
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nop |
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/* Check cputypval[4] to find the sun model */ |
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ldub [%o2 + 0x4], %l1 |
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cmp %l1, 'm' |
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be sun4m_init |
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cmp %l1, 's' |
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be sun4m_init |
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cmp %l1, 'd' |
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be sun4d_init |
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cmp %l1, 'e' |
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be no_sun4e_here ! Could be a sun4e. |
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nop |
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b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :)) |
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nop |
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leon_init: |
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/* LEON CPU - set boot_cpu_id */ |
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sethi %hi(boot_cpu_id), %g2 ! boot-cpu index |
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#ifdef CONFIG_SMP |
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ldub [%g2 + %lo(boot_cpu_id)], %g1 |
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cmp %g1, 0xff ! unset means first CPU |
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bne leon_smp_cpu_startup ! continue only with master |
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nop |
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#endif |
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/* Get CPU-ID from most significant 4-bit of ASR17 */ |
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rd %asr17, %g1 |
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srl %g1, 28, %g1 |
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/* Update boot_cpu_id only on boot cpu */ |
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stub %g1, [%g2 + %lo(boot_cpu_id)] |
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ba continue_boot |
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nop |
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/* CPUID in bootbus can be found at PA 0xff0140000 */ |
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#define SUN4D_BOOTBUS_CPUID 0xf0140000 |
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sun4d_init: |
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/* Need to patch call to handler_irq */ |
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set patch_handler_irq, %g4 |
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set sun4d_handler_irq, %g5 |
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sethi %hi(0x40000000), %g3 ! call |
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sub %g5, %g4, %g5 |
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srl %g5, 2, %g5 |
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or %g5, %g3, %g5 |
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st %g5, [%g4] |
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#ifdef CONFIG_SMP |
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/* Get our CPU id out of bootbus */ |
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set SUN4D_BOOTBUS_CPUID, %g3 |
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lduba [%g3] ASI_M_CTL, %g3 |
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and %g3, 0xf8, %g3 |
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srl %g3, 3, %g4 |
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sta %g4, [%g0] ASI_M_VIKING_TMP1 |
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sethi %hi(boot_cpu_id), %g5 |
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stb %g4, [%g5 + %lo(boot_cpu_id)] |
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#endif |
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/* Fall through to sun4m_init */ |
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sun4m_init: |
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/* Ok, the PROM could have done funny things and apple cider could still |
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* be sitting in the fault status/address registers. Read them all to |
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* clear them so we don't get magic faults later on. |
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*/ |
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/* This sucks, apparently this makes Vikings call prom panic, will fix later */ |
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2: |
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rd %psr, %o1 |
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srl %o1, PSR_IMPL_SHIFT, %o1 ! Get a type of the CPU |
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subcc %o1, PSR_IMPL_TI, %g0 ! TI: Viking or MicroSPARC |
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be continue_boot |
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nop |
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set AC_M_SFSR, %o0 |
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lda [%o0] ASI_M_MMUREGS, %g0 |
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set AC_M_SFAR, %o0 |
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lda [%o0] ASI_M_MMUREGS, %g0 |
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/* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */ |
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subcc %o1, 0, %g0 |
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be continue_boot |
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nop |
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set AC_M_AFSR, %o0 |
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lda [%o0] ASI_M_MMUREGS, %g0 |
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set AC_M_AFAR, %o0 |
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lda [%o0] ASI_M_MMUREGS, %g0 |
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nop |
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continue_boot: |
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/* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's |
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* show-time! |
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*/ |
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/* Turn on Supervisor, EnableFloating, and all the PIL bits. |
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* Also puts us in register window zero with traps off. |
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*/ |
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set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2 |
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wr %g2, 0x0, %psr |
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WRITE_PAUSE |
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/* I want a kernel stack NOW! */ |
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set init_thread_union, %g1 |
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set (THREAD_SIZE - STACKFRAME_SZ - TRACEREG_SZ), %g2 |
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add %g1, %g2, %sp |
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mov 0, %fp /* And for good luck */ |
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|
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/* Zero out our BSS section. */ |
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set __bss_start , %o0 ! First address of BSS |
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set _end , %o1 ! Last address of BSS |
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add %o0, 0x1, %o0 |
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1: |
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stb %g0, [%o0] |
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subcc %o0, %o1, %g0 |
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bl 1b |
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add %o0, 0x1, %o0 |
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/* If boot_cpu_id has not been setup by machine specific |
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* init-code above we default it to zero. |
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*/ |
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sethi %hi(boot_cpu_id), %g2 |
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ldub [%g2 + %lo(boot_cpu_id)], %g3 |
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cmp %g3, 0xff |
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bne 1f |
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nop |
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mov %g0, %g3 |
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stub %g3, [%g2 + %lo(boot_cpu_id)] |
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1: sll %g3, 2, %g3 |
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/* Initialize the uwinmask value for init task just in case. |
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* But first make current_set[boot_cpu_id] point to something useful. |
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*/ |
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set init_thread_union, %g6 |
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set current_set, %g2 |
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#ifdef CONFIG_SMP |
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st %g6, [%g2] |
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add %g2, %g3, %g2 |
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#endif |
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st %g6, [%g2] |
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st %g0, [%g6 + TI_UWINMASK] |
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/* Compute NWINDOWS and stash it away. Now uses %wim trick explained |
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* in the V8 manual. Ok, this method seems to work, Sparc is cool... |
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* No, it doesn't work, have to play the save/readCWP/restore trick. |
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*/ |
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wr %g0, 0x0, %wim ! so we do not get a trap |
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WRITE_PAUSE |
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save |
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rd %psr, %g3 |
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restore |
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and %g3, 0x1f, %g3 |
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add %g3, 0x1, %g3 |
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mov 2, %g1 |
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wr %g1, 0x0, %wim ! make window 1 invalid |
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WRITE_PAUSE |
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cmp %g3, 0x7 |
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bne 2f |
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nop |
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/* Adjust our window handling routines to |
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* do things correctly on 7 window Sparcs. |
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*/ |
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#define PATCH_INSN(src, dest) \ |
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set src, %g5; \ |
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set dest, %g2; \ |
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ld [%g5], %g4; \ |
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st %g4, [%g2]; |
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|
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/* Patch for window spills... */ |
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PATCH_INSN(spnwin_patch1_7win, spnwin_patch1) |
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PATCH_INSN(spnwin_patch2_7win, spnwin_patch2) |
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PATCH_INSN(spnwin_patch3_7win, spnwin_patch3) |
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/* Patch for window fills... */ |
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PATCH_INSN(fnwin_patch1_7win, fnwin_patch1) |
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PATCH_INSN(fnwin_patch2_7win, fnwin_patch2) |
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/* Patch for trap entry setup... */ |
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PATCH_INSN(tsetup_7win_patch1, tsetup_patch1) |
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PATCH_INSN(tsetup_7win_patch2, tsetup_patch2) |
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PATCH_INSN(tsetup_7win_patch3, tsetup_patch3) |
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PATCH_INSN(tsetup_7win_patch4, tsetup_patch4) |
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PATCH_INSN(tsetup_7win_patch5, tsetup_patch5) |
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PATCH_INSN(tsetup_7win_patch6, tsetup_patch6) |
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|
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/* Patch for returning from traps... */ |
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PATCH_INSN(rtrap_7win_patch1, rtrap_patch1) |
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PATCH_INSN(rtrap_7win_patch2, rtrap_patch2) |
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PATCH_INSN(rtrap_7win_patch3, rtrap_patch3) |
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PATCH_INSN(rtrap_7win_patch4, rtrap_patch4) |
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PATCH_INSN(rtrap_7win_patch5, rtrap_patch5) |
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/* Patch for killing user windows from the register file. */ |
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PATCH_INSN(kuw_patch1_7win, kuw_patch1) |
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/* Now patch the kernel window flush sequences. |
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* This saves 2 traps on every switch and fork. |
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*/ |
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set 0x01000000, %g4 |
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set flush_patch_one, %g5 |
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st %g4, [%g5 + 0x18] |
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st %g4, [%g5 + 0x1c] |
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set flush_patch_two, %g5 |
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st %g4, [%g5 + 0x18] |
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st %g4, [%g5 + 0x1c] |
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set flush_patch_three, %g5 |
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st %g4, [%g5 + 0x18] |
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st %g4, [%g5 + 0x1c] |
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set flush_patch_four, %g5 |
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st %g4, [%g5 + 0x18] |
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st %g4, [%g5 + 0x1c] |
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set flush_patch_exception, %g5 |
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st %g4, [%g5 + 0x18] |
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st %g4, [%g5 + 0x1c] |
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set flush_patch_switch, %g5 |
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st %g4, [%g5 + 0x18] |
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st %g4, [%g5 + 0x1c] |
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2: |
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sethi %hi(nwindows), %g4 |
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st %g3, [%g4 + %lo(nwindows)] ! store final value |
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sub %g3, 0x1, %g3 |
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sethi %hi(nwindowsm1), %g4 |
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st %g3, [%g4 + %lo(nwindowsm1)] |
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/* Here we go, start using Linux's trap table... */ |
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set trapbase, %g3 |
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wr %g3, 0x0, %tbr |
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WRITE_PAUSE |
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/* Finally, turn on traps so that we can call c-code. */ |
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rd %psr, %g3 |
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wr %g3, 0x0, %psr |
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WRITE_PAUSE |
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|
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wr %g3, PSR_ET, %psr |
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WRITE_PAUSE |
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/* Call sparc32_start_kernel(struct linux_romvec *rp) */ |
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sethi %hi(prom_vector_p), %g5 |
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ld [%g5 + %lo(prom_vector_p)], %o0 |
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call sparc32_start_kernel |
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nop |
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/* We should not get here. */ |
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call halt_me |
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nop |
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no_sun4e_here: |
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ld [%g7 + 0x68], %o1 |
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set sun4e_notsup, %o0 |
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call %o1 |
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nop |
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b halt_me |
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nop |
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__INITDATA |
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sun4u_1: |
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.asciz "finddevice" |
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.align 4 |
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sun4u_2: |
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.asciz "/chosen" |
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.align 4 |
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sun4u_3: |
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.asciz "getprop" |
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.align 4 |
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sun4u_4: |
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.asciz "stdout" |
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.align 4 |
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sun4u_5: |
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.asciz "write" |
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.align 4 |
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sun4u_6: |
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.asciz "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r" |
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sun4u_6e: |
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.align 4 |
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sun4u_7: |
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.asciz "exit" |
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.align 8 |
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sun4u_a1: |
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.word 0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0 |
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sun4u_r1: |
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.word 0 |
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sun4u_a2: |
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.word 0, sun4u_3, 0, 4, 0, 1, 0 |
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sun4u_i2: |
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.word 0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0 |
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sun4u_r2: |
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.word 0 |
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sun4u_a3: |
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.word 0, sun4u_5, 0, 3, 0, 1, 0 |
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sun4u_i3: |
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.word 0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0 |
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sun4u_r3: |
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.word 0 |
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sun4u_a4: |
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.word 0, sun4u_7, 0, 0, 0, 0 |
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sun4u_r4: |
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__INIT |
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no_sun4u_here: |
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set sun4u_a1, %o0 |
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set current_pc, %l2 |
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cmp %l2, %g3 |
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be 1f |
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mov %o4, %l0 |
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sub %g3, %l2, %l6 |
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add %o0, %l6, %o0 |
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mov %o0, %l4 |
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mov sun4u_r4 - sun4u_a1, %l3 |
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ld [%l4], %l5 |
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2: |
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add %l4, 4, %l4 |
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cmp %l5, %l2 |
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add %l5, %l6, %l5 |
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bgeu,a 3f |
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st %l5, [%l4 - 4] |
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3: |
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subcc %l3, 4, %l3 |
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bne 2b |
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ld [%l4], %l5 |
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1: |
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call %l0 |
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mov %o0, %l1 |
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|
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ld [%l1 + (sun4u_r1 - sun4u_a1)], %o1 |
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add %l1, (sun4u_a2 - sun4u_a1), %o0 |
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call %l0 |
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st %o1, [%o0 + (sun4u_i2 - sun4u_a2)] |
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|
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ld [%l1 + (sun4u_1 - sun4u_a1)], %o1 |
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add %l1, (sun4u_a3 - sun4u_a1), %o0 |
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call %l0 |
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st %o1, [%o0 + (sun4u_i3 - sun4u_a3)] |
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|
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call %l0 |
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add %l1, (sun4u_a4 - sun4u_a1), %o0 |
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|
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/* Not reached */ |
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halt_me: |
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ld [%g7 + 0x74], %o0 |
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call %o0 ! Get us out of here... |
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nop ! Apparently Solaris is better. |
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|
|
/* Ok, now we continue in the .data/.text sections */ |
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|
|
.data |
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.align 4 |
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|
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/* |
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* Fill up the prom vector, note in particular the kind first element, |
|
* no joke. I don't need all of them in here as the entire prom vector |
|
* gets initialized in c-code so all routines can use it. |
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*/ |
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|
prom_vector_p: |
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.word 0 |
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|
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/* We calculate the following at boot time, window fills/spills and trap entry |
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* code uses these to keep track of the register windows. |
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*/ |
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|
|
.align 4 |
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.globl nwindows |
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.globl nwindowsm1 |
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nwindows: |
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.word 8 |
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nwindowsm1: |
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.word 7 |
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|
|
/* Boot time debugger vector value. We need this later on. */ |
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|
|
.align 4 |
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.globl linux_dbvec |
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linux_dbvec: |
|
.word 0 |
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.word 0 |
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|
|
.align 8 |
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|
|
.globl lvl14_save |
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lvl14_save: |
|
.word 0 |
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.word 0 |
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.word 0 |
|
.word 0 |
|
.word t_irq14
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|
|