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864 lines
20 KiB
864 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* chmc.c: Driver for UltraSPARC-III memory controller. |
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* |
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* Copyright (C) 2001, 2007, 2008 David S. Miller ([email protected]) |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/slab.h> |
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#include <linux/list.h> |
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#include <linux/string.h> |
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#include <linux/sched.h> |
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#include <linux/smp.h> |
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#include <linux/errno.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <asm/spitfire.h> |
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#include <asm/chmctrl.h> |
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#include <asm/cpudata.h> |
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#include <asm/oplib.h> |
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#include <asm/prom.h> |
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#include <asm/head.h> |
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#include <asm/io.h> |
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#include <asm/memctrl.h> |
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#define DRV_MODULE_NAME "chmc" |
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#define PFX DRV_MODULE_NAME ": " |
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#define DRV_MODULE_VERSION "0.2" |
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MODULE_AUTHOR("David S. Miller ([email protected])"); |
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MODULE_DESCRIPTION("UltraSPARC-III memory controller driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_VERSION(DRV_MODULE_VERSION); |
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static int mc_type; |
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#define MC_TYPE_SAFARI 1 |
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#define MC_TYPE_JBUS 2 |
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static dimm_printer_t us3mc_dimm_printer; |
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#define CHMCTRL_NDGRPS 2 |
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#define CHMCTRL_NDIMMS 4 |
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#define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS) |
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/* OBP memory-layout property format. */ |
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struct chmc_obp_map { |
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unsigned char dimm_map[144]; |
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unsigned char pin_map[576]; |
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}; |
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#define DIMM_LABEL_SZ 8 |
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struct chmc_obp_mem_layout { |
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/* One max 8-byte string label per DIMM. Usually |
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* this matches the label on the motherboard where |
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* that DIMM resides. |
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*/ |
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char dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ]; |
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/* If symmetric use map[0], else it is |
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* asymmetric and map[1] should be used. |
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*/ |
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char symmetric; |
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struct chmc_obp_map map[2]; |
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}; |
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#define CHMCTRL_NBANKS 4 |
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struct chmc_bank_info { |
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struct chmc *p; |
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int bank_id; |
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u64 raw_reg; |
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int valid; |
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int uk; |
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int um; |
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int lk; |
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int lm; |
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int interleave; |
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unsigned long base; |
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unsigned long size; |
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}; |
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struct chmc { |
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struct list_head list; |
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int portid; |
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struct chmc_obp_mem_layout layout_prop; |
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int layout_size; |
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void __iomem *regs; |
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u64 timing_control1; |
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u64 timing_control2; |
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u64 timing_control3; |
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u64 timing_control4; |
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u64 memaddr_control; |
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struct chmc_bank_info logical_banks[CHMCTRL_NBANKS]; |
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}; |
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#define JBUSMC_REGS_SIZE 8 |
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#define JB_MC_REG1_DIMM2_BANK3 0x8000000000000000UL |
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#define JB_MC_REG1_DIMM1_BANK1 0x4000000000000000UL |
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#define JB_MC_REG1_DIMM2_BANK2 0x2000000000000000UL |
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#define JB_MC_REG1_DIMM1_BANK0 0x1000000000000000UL |
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#define JB_MC_REG1_XOR 0x0000010000000000UL |
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#define JB_MC_REG1_ADDR_GEN_2 0x000000e000000000UL |
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#define JB_MC_REG1_ADDR_GEN_2_SHIFT 37 |
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#define JB_MC_REG1_ADDR_GEN_1 0x0000001c00000000UL |
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#define JB_MC_REG1_ADDR_GEN_1_SHIFT 34 |
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#define JB_MC_REG1_INTERLEAVE 0x0000000001800000UL |
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#define JB_MC_REG1_INTERLEAVE_SHIFT 23 |
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#define JB_MC_REG1_DIMM2_PTYPE 0x0000000000200000UL |
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#define JB_MC_REG1_DIMM2_PTYPE_SHIFT 21 |
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#define JB_MC_REG1_DIMM1_PTYPE 0x0000000000100000UL |
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#define JB_MC_REG1_DIMM1_PTYPE_SHIFT 20 |
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#define PART_TYPE_X8 0 |
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#define PART_TYPE_X4 1 |
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#define INTERLEAVE_NONE 0 |
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#define INTERLEAVE_SAME 1 |
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#define INTERLEAVE_INTERNAL 2 |
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#define INTERLEAVE_BOTH 3 |
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#define ADDR_GEN_128MB 0 |
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#define ADDR_GEN_256MB 1 |
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#define ADDR_GEN_512MB 2 |
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#define ADDR_GEN_1GB 3 |
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#define JB_NUM_DIMM_GROUPS 2 |
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#define JB_NUM_DIMMS_PER_GROUP 2 |
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#define JB_NUM_DIMMS (JB_NUM_DIMM_GROUPS * JB_NUM_DIMMS_PER_GROUP) |
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struct jbusmc_obp_map { |
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unsigned char dimm_map[18]; |
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unsigned char pin_map[144]; |
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}; |
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struct jbusmc_obp_mem_layout { |
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/* One max 8-byte string label per DIMM. Usually |
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* this matches the label on the motherboard where |
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* that DIMM resides. |
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*/ |
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char dimm_labels[JB_NUM_DIMMS][DIMM_LABEL_SZ]; |
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/* If symmetric use map[0], else it is |
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* asymmetric and map[1] should be used. |
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*/ |
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char symmetric; |
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struct jbusmc_obp_map map; |
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char _pad; |
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}; |
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struct jbusmc_dimm_group { |
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struct jbusmc *controller; |
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int index; |
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u64 base_addr; |
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u64 size; |
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}; |
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struct jbusmc { |
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void __iomem *regs; |
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u64 mc_reg_1; |
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u32 portid; |
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struct jbusmc_obp_mem_layout layout; |
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int layout_len; |
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int num_dimm_groups; |
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struct jbusmc_dimm_group dimm_groups[JB_NUM_DIMM_GROUPS]; |
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struct list_head list; |
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}; |
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static DEFINE_SPINLOCK(mctrl_list_lock); |
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static LIST_HEAD(mctrl_list); |
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static void mc_list_add(struct list_head *list) |
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{ |
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spin_lock(&mctrl_list_lock); |
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list_add(list, &mctrl_list); |
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spin_unlock(&mctrl_list_lock); |
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} |
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static void mc_list_del(struct list_head *list) |
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{ |
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spin_lock(&mctrl_list_lock); |
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list_del_init(list); |
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spin_unlock(&mctrl_list_lock); |
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} |
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#define SYNDROME_MIN -1 |
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#define SYNDROME_MAX 144 |
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/* Covert syndrome code into the way the bits are positioned |
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* on the bus. |
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*/ |
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static int syndrome_to_qword_code(int syndrome_code) |
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{ |
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if (syndrome_code < 128) |
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syndrome_code += 16; |
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else if (syndrome_code < 128 + 9) |
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syndrome_code -= (128 - 7); |
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else if (syndrome_code < (128 + 9 + 3)) |
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syndrome_code -= (128 + 9 - 4); |
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else |
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syndrome_code -= (128 + 9 + 3); |
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return syndrome_code; |
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} |
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/* All this magic has to do with how a cache line comes over the wire |
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* on Safari and JBUS. A 64-bit line comes over in 1 or more quadword |
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* cycles, each of which transmit ECC/MTAG info as well as the actual |
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* data. |
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*/ |
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#define L2_LINE_SIZE 64 |
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#define L2_LINE_ADDR_MSK (L2_LINE_SIZE - 1) |
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#define QW_PER_LINE 4 |
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#define QW_BYTES (L2_LINE_SIZE / QW_PER_LINE) |
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#define QW_BITS 144 |
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#define SAFARI_LAST_BIT (576 - 1) |
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#define JBUS_LAST_BIT (144 - 1) |
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static void get_pin_and_dimm_str(int syndrome_code, unsigned long paddr, |
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int *pin_p, char **dimm_str_p, void *_prop, |
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int base_dimm_offset) |
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{ |
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int qword_code = syndrome_to_qword_code(syndrome_code); |
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int cache_line_offset; |
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int offset_inverse; |
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int dimm_map_index; |
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int map_val; |
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if (mc_type == MC_TYPE_JBUS) { |
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struct jbusmc_obp_mem_layout *p = _prop; |
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/* JBUS */ |
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cache_line_offset = qword_code; |
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offset_inverse = (JBUS_LAST_BIT - cache_line_offset); |
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dimm_map_index = offset_inverse / 8; |
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map_val = p->map.dimm_map[dimm_map_index]; |
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map_val = ((map_val >> ((7 - (offset_inverse & 7)))) & 1); |
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*dimm_str_p = p->dimm_labels[base_dimm_offset + map_val]; |
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*pin_p = p->map.pin_map[cache_line_offset]; |
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} else { |
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struct chmc_obp_mem_layout *p = _prop; |
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struct chmc_obp_map *mp; |
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int qword; |
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/* Safari */ |
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if (p->symmetric) |
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mp = &p->map[0]; |
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else |
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mp = &p->map[1]; |
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qword = (paddr & L2_LINE_ADDR_MSK) / QW_BYTES; |
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cache_line_offset = ((3 - qword) * QW_BITS) + qword_code; |
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offset_inverse = (SAFARI_LAST_BIT - cache_line_offset); |
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dimm_map_index = offset_inverse >> 2; |
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map_val = mp->dimm_map[dimm_map_index]; |
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map_val = ((map_val >> ((3 - (offset_inverse & 3)) << 1)) & 0x3); |
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*dimm_str_p = p->dimm_labels[base_dimm_offset + map_val]; |
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*pin_p = mp->pin_map[cache_line_offset]; |
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} |
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} |
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static struct jbusmc_dimm_group *jbusmc_find_dimm_group(unsigned long phys_addr) |
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{ |
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struct jbusmc *p; |
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list_for_each_entry(p, &mctrl_list, list) { |
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int i; |
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for (i = 0; i < p->num_dimm_groups; i++) { |
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struct jbusmc_dimm_group *dp = &p->dimm_groups[i]; |
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if (phys_addr < dp->base_addr || |
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(dp->base_addr + dp->size) <= phys_addr) |
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continue; |
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return dp; |
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} |
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} |
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return NULL; |
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} |
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static int jbusmc_print_dimm(int syndrome_code, |
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unsigned long phys_addr, |
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char *buf, int buflen) |
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{ |
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struct jbusmc_obp_mem_layout *prop; |
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struct jbusmc_dimm_group *dp; |
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struct jbusmc *p; |
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int first_dimm; |
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dp = jbusmc_find_dimm_group(phys_addr); |
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if (dp == NULL || |
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syndrome_code < SYNDROME_MIN || |
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syndrome_code > SYNDROME_MAX) { |
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buf[0] = '?'; |
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buf[1] = '?'; |
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buf[2] = '?'; |
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buf[3] = '\0'; |
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return 0; |
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} |
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p = dp->controller; |
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prop = &p->layout; |
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first_dimm = dp->index * JB_NUM_DIMMS_PER_GROUP; |
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if (syndrome_code != SYNDROME_MIN) { |
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char *dimm_str; |
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int pin; |
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get_pin_and_dimm_str(syndrome_code, phys_addr, &pin, |
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&dimm_str, prop, first_dimm); |
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sprintf(buf, "%s, pin %3d", dimm_str, pin); |
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} else { |
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int dimm; |
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/* Multi-bit error, we just dump out all the |
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* dimm labels associated with this dimm group. |
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*/ |
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for (dimm = 0; dimm < JB_NUM_DIMMS_PER_GROUP; dimm++) { |
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sprintf(buf, "%s ", |
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prop->dimm_labels[first_dimm + dimm]); |
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buf += strlen(buf); |
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} |
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} |
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return 0; |
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} |
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static u64 jbusmc_dimm_group_size(u64 base, |
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const struct linux_prom64_registers *mem_regs, |
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int num_mem_regs) |
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{ |
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u64 max = base + (8UL * 1024 * 1024 * 1024); |
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u64 max_seen = base; |
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int i; |
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for (i = 0; i < num_mem_regs; i++) { |
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const struct linux_prom64_registers *ent; |
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u64 this_base; |
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u64 this_end; |
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ent = &mem_regs[i]; |
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this_base = ent->phys_addr; |
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this_end = this_base + ent->reg_size; |
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if (base < this_base || base >= this_end) |
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continue; |
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if (this_end > max) |
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this_end = max; |
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if (this_end > max_seen) |
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max_seen = this_end; |
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} |
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return max_seen - base; |
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} |
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static void jbusmc_construct_one_dimm_group(struct jbusmc *p, |
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unsigned long index, |
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const struct linux_prom64_registers *mem_regs, |
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int num_mem_regs) |
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{ |
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struct jbusmc_dimm_group *dp = &p->dimm_groups[index]; |
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dp->controller = p; |
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dp->index = index; |
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dp->base_addr = (p->portid * (64UL * 1024 * 1024 * 1024)); |
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dp->base_addr += (index * (8UL * 1024 * 1024 * 1024)); |
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dp->size = jbusmc_dimm_group_size(dp->base_addr, mem_regs, num_mem_regs); |
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} |
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static void jbusmc_construct_dimm_groups(struct jbusmc *p, |
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const struct linux_prom64_registers *mem_regs, |
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int num_mem_regs) |
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{ |
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if (p->mc_reg_1 & JB_MC_REG1_DIMM1_BANK0) { |
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jbusmc_construct_one_dimm_group(p, 0, mem_regs, num_mem_regs); |
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p->num_dimm_groups++; |
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} |
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if (p->mc_reg_1 & JB_MC_REG1_DIMM2_BANK2) { |
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jbusmc_construct_one_dimm_group(p, 1, mem_regs, num_mem_regs); |
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p->num_dimm_groups++; |
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} |
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} |
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static int jbusmc_probe(struct platform_device *op) |
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{ |
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const struct linux_prom64_registers *mem_regs; |
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struct device_node *mem_node; |
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int err, len, num_mem_regs; |
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struct jbusmc *p; |
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const u32 *prop; |
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const void *ml; |
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err = -ENODEV; |
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mem_node = of_find_node_by_path("/memory"); |
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if (!mem_node) { |
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printk(KERN_ERR PFX "Cannot find /memory node.\n"); |
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goto out; |
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} |
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mem_regs = of_get_property(mem_node, "reg", &len); |
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if (!mem_regs) { |
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printk(KERN_ERR PFX "Cannot get reg property of /memory node.\n"); |
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goto out; |
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} |
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num_mem_regs = len / sizeof(*mem_regs); |
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err = -ENOMEM; |
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p = kzalloc(sizeof(*p), GFP_KERNEL); |
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if (!p) { |
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printk(KERN_ERR PFX "Cannot allocate struct jbusmc.\n"); |
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goto out; |
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} |
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INIT_LIST_HEAD(&p->list); |
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err = -ENODEV; |
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prop = of_get_property(op->dev.of_node, "portid", &len); |
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if (!prop || len != 4) { |
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printk(KERN_ERR PFX "Cannot find portid.\n"); |
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goto out_free; |
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} |
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p->portid = *prop; |
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prop = of_get_property(op->dev.of_node, "memory-control-register-1", &len); |
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if (!prop || len != 8) { |
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printk(KERN_ERR PFX "Cannot get memory control register 1.\n"); |
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goto out_free; |
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} |
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p->mc_reg_1 = ((u64)prop[0] << 32) | (u64) prop[1]; |
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err = -ENOMEM; |
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p->regs = of_ioremap(&op->resource[0], 0, JBUSMC_REGS_SIZE, "jbusmc"); |
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if (!p->regs) { |
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printk(KERN_ERR PFX "Cannot map jbusmc regs.\n"); |
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goto out_free; |
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} |
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err = -ENODEV; |
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ml = of_get_property(op->dev.of_node, "memory-layout", &p->layout_len); |
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if (!ml) { |
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printk(KERN_ERR PFX "Cannot get memory layout property.\n"); |
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goto out_iounmap; |
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} |
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if (p->layout_len > sizeof(p->layout)) { |
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printk(KERN_ERR PFX "Unexpected memory-layout size %d\n", |
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p->layout_len); |
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goto out_iounmap; |
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} |
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memcpy(&p->layout, ml, p->layout_len); |
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jbusmc_construct_dimm_groups(p, mem_regs, num_mem_regs); |
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mc_list_add(&p->list); |
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printk(KERN_INFO PFX "UltraSPARC-IIIi memory controller at %pOF\n", |
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op->dev.of_node); |
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dev_set_drvdata(&op->dev, p); |
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err = 0; |
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out: |
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return err; |
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out_iounmap: |
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of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE); |
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out_free: |
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kfree(p); |
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goto out; |
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} |
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/* Does BANK decode PHYS_ADDR? */ |
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static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr) |
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{ |
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unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT; |
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unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT; |
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/* Bank must be enabled to match. */ |
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if (bp->valid == 0) |
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return 0; |
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/* Would BANK match upper bits? */ |
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upper_bits ^= bp->um; /* What bits are different? */ |
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upper_bits = ~upper_bits; /* Invert. */ |
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upper_bits |= bp->uk; /* What bits don't matter for matching? */ |
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upper_bits = ~upper_bits; /* Invert. */ |
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if (upper_bits) |
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return 0; |
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/* Would BANK match lower bits? */ |
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lower_bits ^= bp->lm; /* What bits are different? */ |
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lower_bits = ~lower_bits; /* Invert. */ |
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lower_bits |= bp->lk; /* What bits don't matter for matching? */ |
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lower_bits = ~lower_bits; /* Invert. */ |
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if (lower_bits) |
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return 0; |
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/* I always knew you'd be the one. */ |
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return 1; |
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} |
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/* Given PHYS_ADDR, search memory controller banks for a match. */ |
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static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr) |
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{ |
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struct chmc *p; |
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list_for_each_entry(p, &mctrl_list, list) { |
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int bank_no; |
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for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) { |
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struct chmc_bank_info *bp; |
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bp = &p->logical_banks[bank_no]; |
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if (chmc_bank_match(bp, phys_addr)) |
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return bp; |
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} |
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} |
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return NULL; |
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} |
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/* This is the main purpose of this driver. */ |
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static int chmc_print_dimm(int syndrome_code, |
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unsigned long phys_addr, |
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char *buf, int buflen) |
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{ |
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struct chmc_bank_info *bp; |
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struct chmc_obp_mem_layout *prop; |
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int bank_in_controller, first_dimm; |
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bp = chmc_find_bank(phys_addr); |
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if (bp == NULL || |
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syndrome_code < SYNDROME_MIN || |
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syndrome_code > SYNDROME_MAX) { |
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buf[0] = '?'; |
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buf[1] = '?'; |
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buf[2] = '?'; |
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buf[3] = '\0'; |
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return 0; |
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} |
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prop = &bp->p->layout_prop; |
|
bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1); |
|
first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1)); |
|
first_dimm *= CHMCTRL_NDIMMS; |
|
|
|
if (syndrome_code != SYNDROME_MIN) { |
|
char *dimm_str; |
|
int pin; |
|
|
|
get_pin_and_dimm_str(syndrome_code, phys_addr, &pin, |
|
&dimm_str, prop, first_dimm); |
|
sprintf(buf, "%s, pin %3d", dimm_str, pin); |
|
} else { |
|
int dimm; |
|
|
|
/* Multi-bit error, we just dump out all the |
|
* dimm labels associated with this bank. |
|
*/ |
|
for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) { |
|
sprintf(buf, "%s ", |
|
prop->dimm_labels[first_dimm + dimm]); |
|
buf += strlen(buf); |
|
} |
|
} |
|
return 0; |
|
} |
|
|
|
/* Accessing the registers is slightly complicated. If you want |
|
* to get at the memory controller which is on the same processor |
|
* the code is executing, you must use special ASI load/store else |
|
* you go through the global mapping. |
|
*/ |
|
static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset) |
|
{ |
|
unsigned long ret, this_cpu; |
|
|
|
preempt_disable(); |
|
|
|
this_cpu = real_hard_smp_processor_id(); |
|
|
|
if (p->portid == this_cpu) { |
|
__asm__ __volatile__("ldxa [%1] %2, %0" |
|
: "=r" (ret) |
|
: "r" (offset), "i" (ASI_MCU_CTRL_REG)); |
|
} else { |
|
__asm__ __volatile__("ldxa [%1] %2, %0" |
|
: "=r" (ret) |
|
: "r" (p->regs + offset), |
|
"i" (ASI_PHYS_BYPASS_EC_E)); |
|
} |
|
|
|
preempt_enable(); |
|
|
|
return ret; |
|
} |
|
|
|
#if 0 /* currently unused */ |
|
static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val) |
|
{ |
|
if (p->portid == smp_processor_id()) { |
|
__asm__ __volatile__("stxa %0, [%1] %2" |
|
: : "r" (val), |
|
"r" (offset), "i" (ASI_MCU_CTRL_REG)); |
|
} else { |
|
__asm__ __volatile__("ldxa %0, [%1] %2" |
|
: : "r" (val), |
|
"r" (p->regs + offset), |
|
"i" (ASI_PHYS_BYPASS_EC_E)); |
|
} |
|
} |
|
#endif |
|
|
|
static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val) |
|
{ |
|
struct chmc_bank_info *bp = &p->logical_banks[which_bank]; |
|
|
|
bp->p = p; |
|
bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank; |
|
bp->raw_reg = val; |
|
bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT; |
|
bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT; |
|
bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT; |
|
bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT; |
|
bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT; |
|
|
|
bp->base = (bp->um); |
|
bp->base &= ~(bp->uk); |
|
bp->base <<= PA_UPPER_BITS_SHIFT; |
|
|
|
switch(bp->lk) { |
|
case 0xf: |
|
default: |
|
bp->interleave = 1; |
|
break; |
|
|
|
case 0xe: |
|
bp->interleave = 2; |
|
break; |
|
|
|
case 0xc: |
|
bp->interleave = 4; |
|
break; |
|
|
|
case 0x8: |
|
bp->interleave = 8; |
|
break; |
|
|
|
case 0x0: |
|
bp->interleave = 16; |
|
break; |
|
} |
|
|
|
/* UK[10] is reserved, and UK[11] is not set for the SDRAM |
|
* bank size definition. |
|
*/ |
|
bp->size = (((unsigned long)bp->uk & |
|
((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT; |
|
bp->size /= bp->interleave; |
|
} |
|
|
|
static void chmc_fetch_decode_regs(struct chmc *p) |
|
{ |
|
if (p->layout_size == 0) |
|
return; |
|
|
|
chmc_interpret_one_decode_reg(p, 0, |
|
chmc_read_mcreg(p, CHMCTRL_DECODE1)); |
|
chmc_interpret_one_decode_reg(p, 1, |
|
chmc_read_mcreg(p, CHMCTRL_DECODE2)); |
|
chmc_interpret_one_decode_reg(p, 2, |
|
chmc_read_mcreg(p, CHMCTRL_DECODE3)); |
|
chmc_interpret_one_decode_reg(p, 3, |
|
chmc_read_mcreg(p, CHMCTRL_DECODE4)); |
|
} |
|
|
|
static int chmc_probe(struct platform_device *op) |
|
{ |
|
struct device_node *dp = op->dev.of_node; |
|
unsigned long ver; |
|
const void *pval; |
|
int len, portid; |
|
struct chmc *p; |
|
int err; |
|
|
|
err = -ENODEV; |
|
__asm__ ("rdpr %%ver, %0" : "=r" (ver)); |
|
if ((ver >> 32UL) == __JALAPENO_ID || |
|
(ver >> 32UL) == __SERRANO_ID) |
|
goto out; |
|
|
|
portid = of_getintprop_default(dp, "portid", -1); |
|
if (portid == -1) |
|
goto out; |
|
|
|
pval = of_get_property(dp, "memory-layout", &len); |
|
if (pval && len > sizeof(p->layout_prop)) { |
|
printk(KERN_ERR PFX "Unexpected memory-layout property " |
|
"size %d.\n", len); |
|
goto out; |
|
} |
|
|
|
err = -ENOMEM; |
|
p = kzalloc(sizeof(*p), GFP_KERNEL); |
|
if (!p) { |
|
printk(KERN_ERR PFX "Could not allocate struct chmc.\n"); |
|
goto out; |
|
} |
|
|
|
p->portid = portid; |
|
p->layout_size = len; |
|
if (!pval) |
|
p->layout_size = 0; |
|
else |
|
memcpy(&p->layout_prop, pval, len); |
|
|
|
p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc"); |
|
if (!p->regs) { |
|
printk(KERN_ERR PFX "Could not map registers.\n"); |
|
goto out_free; |
|
} |
|
|
|
if (p->layout_size != 0UL) { |
|
p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1); |
|
p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2); |
|
p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3); |
|
p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4); |
|
p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL); |
|
} |
|
|
|
chmc_fetch_decode_regs(p); |
|
|
|
mc_list_add(&p->list); |
|
|
|
printk(KERN_INFO PFX "UltraSPARC-III memory controller at %pOF [%s]\n", |
|
dp, |
|
(p->layout_size ? "ACTIVE" : "INACTIVE")); |
|
|
|
dev_set_drvdata(&op->dev, p); |
|
|
|
err = 0; |
|
|
|
out: |
|
return err; |
|
|
|
out_free: |
|
kfree(p); |
|
goto out; |
|
} |
|
|
|
static int us3mc_probe(struct platform_device *op) |
|
{ |
|
if (mc_type == MC_TYPE_SAFARI) |
|
return chmc_probe(op); |
|
else if (mc_type == MC_TYPE_JBUS) |
|
return jbusmc_probe(op); |
|
return -ENODEV; |
|
} |
|
|
|
static void chmc_destroy(struct platform_device *op, struct chmc *p) |
|
{ |
|
list_del(&p->list); |
|
of_iounmap(&op->resource[0], p->regs, 0x48); |
|
kfree(p); |
|
} |
|
|
|
static void jbusmc_destroy(struct platform_device *op, struct jbusmc *p) |
|
{ |
|
mc_list_del(&p->list); |
|
of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE); |
|
kfree(p); |
|
} |
|
|
|
static int us3mc_remove(struct platform_device *op) |
|
{ |
|
void *p = dev_get_drvdata(&op->dev); |
|
|
|
if (p) { |
|
if (mc_type == MC_TYPE_SAFARI) |
|
chmc_destroy(op, p); |
|
else if (mc_type == MC_TYPE_JBUS) |
|
jbusmc_destroy(op, p); |
|
} |
|
return 0; |
|
} |
|
|
|
static const struct of_device_id us3mc_match[] = { |
|
{ |
|
.name = "memory-controller", |
|
}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, us3mc_match); |
|
|
|
static struct platform_driver us3mc_driver = { |
|
.driver = { |
|
.name = "us3mc", |
|
.of_match_table = us3mc_match, |
|
}, |
|
.probe = us3mc_probe, |
|
.remove = us3mc_remove, |
|
}; |
|
|
|
static inline bool us3mc_platform(void) |
|
{ |
|
if (tlb_type == cheetah || tlb_type == cheetah_plus) |
|
return true; |
|
return false; |
|
} |
|
|
|
static int __init us3mc_init(void) |
|
{ |
|
unsigned long ver; |
|
int ret; |
|
|
|
if (!us3mc_platform()) |
|
return -ENODEV; |
|
|
|
__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); |
|
if ((ver >> 32UL) == __JALAPENO_ID || |
|
(ver >> 32UL) == __SERRANO_ID) { |
|
mc_type = MC_TYPE_JBUS; |
|
us3mc_dimm_printer = jbusmc_print_dimm; |
|
} else { |
|
mc_type = MC_TYPE_SAFARI; |
|
us3mc_dimm_printer = chmc_print_dimm; |
|
} |
|
|
|
ret = register_dimm_printer(us3mc_dimm_printer); |
|
|
|
if (!ret) { |
|
ret = platform_driver_register(&us3mc_driver); |
|
if (ret) |
|
unregister_dimm_printer(us3mc_dimm_printer); |
|
} |
|
return ret; |
|
} |
|
|
|
static void __exit us3mc_cleanup(void) |
|
{ |
|
if (us3mc_platform()) { |
|
unregister_dimm_printer(us3mc_dimm_printer); |
|
platform_driver_unregister(&us3mc_driver); |
|
} |
|
} |
|
|
|
module_init(us3mc_init); |
|
module_exit(us3mc_cleanup);
|
|
|