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217 lines
6.6 KiB
217 lines
6.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _SPARC_TRAP_BLOCK_H |
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#define _SPARC_TRAP_BLOCK_H |
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#include <linux/threads.h> |
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#include <asm/hypervisor.h> |
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#include <asm/asi.h> |
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#ifndef __ASSEMBLY__ |
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/* Trap handling code needs to get at a few critical values upon |
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* trap entry and to process TSB misses. These cannot be in the |
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* per_cpu() area as we really need to lock them into the TLB and |
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* thus make them part of the main kernel image. As a result we |
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* try to make this as small as possible. |
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* |
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* This is padded out and aligned to 64-bytes to avoid false sharing |
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* on SMP. |
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*/ |
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/* If you modify the size of this structure, please update |
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* TRAP_BLOCK_SZ_SHIFT below. |
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*/ |
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struct thread_info; |
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struct trap_per_cpu { |
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/* D-cache line 1: Basic thread information, cpu and device mondo queues */ |
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struct thread_info *thread; |
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unsigned long pgd_paddr; |
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unsigned long cpu_mondo_pa; |
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unsigned long dev_mondo_pa; |
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/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */ |
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unsigned long resum_mondo_pa; |
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unsigned long resum_kernel_buf_pa; |
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unsigned long nonresum_mondo_pa; |
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unsigned long nonresum_kernel_buf_pa; |
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/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */ |
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struct hv_fault_status fault_info; |
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/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */ |
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unsigned long cpu_mondo_block_pa; |
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unsigned long cpu_list_pa; |
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unsigned long tsb_huge; |
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unsigned long tsb_huge_temp; |
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/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */ |
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unsigned long irq_worklist_pa; |
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unsigned int cpu_mondo_qmask; |
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unsigned int dev_mondo_qmask; |
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unsigned int resum_qmask; |
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unsigned int nonresum_qmask; |
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unsigned long __per_cpu_base; |
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} __attribute__((aligned(64))); |
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extern struct trap_per_cpu trap_block[NR_CPUS]; |
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void init_cur_cpu_trap(struct thread_info *); |
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void setup_tba(void); |
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extern int ncpus_probed; |
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extern u64 cpu_mondo_counter[NR_CPUS]; |
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unsigned long real_hard_smp_processor_id(void); |
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struct cpuid_patch_entry { |
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unsigned int addr; |
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unsigned int cheetah_safari[4]; |
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unsigned int cheetah_jbus[4]; |
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unsigned int starfire[4]; |
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unsigned int sun4v[4]; |
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}; |
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extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end; |
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struct sun4v_1insn_patch_entry { |
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unsigned int addr; |
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unsigned int insn; |
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}; |
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extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch, |
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__sun4v_1insn_patch_end; |
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extern struct sun4v_1insn_patch_entry __fast_win_ctrl_1insn_patch, |
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__fast_win_ctrl_1insn_patch_end; |
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extern struct sun4v_1insn_patch_entry __sun_m7_1insn_patch, |
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__sun_m7_1insn_patch_end; |
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struct sun4v_2insn_patch_entry { |
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unsigned int addr; |
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unsigned int insns[2]; |
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}; |
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extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch, |
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__sun4v_2insn_patch_end; |
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extern struct sun4v_2insn_patch_entry __sun_m7_2insn_patch, |
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__sun_m7_2insn_patch_end; |
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#endif /* !(__ASSEMBLY__) */ |
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#define TRAP_PER_CPU_THREAD 0x00 |
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#define TRAP_PER_CPU_PGD_PADDR 0x08 |
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#define TRAP_PER_CPU_CPU_MONDO_PA 0x10 |
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#define TRAP_PER_CPU_DEV_MONDO_PA 0x18 |
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#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20 |
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#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28 |
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#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30 |
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#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38 |
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#define TRAP_PER_CPU_FAULT_INFO 0x40 |
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#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0 |
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#define TRAP_PER_CPU_CPU_LIST_PA 0xc8 |
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#define TRAP_PER_CPU_TSB_HUGE 0xd0 |
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#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8 |
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#define TRAP_PER_CPU_IRQ_WORKLIST_PA 0xe0 |
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#define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe8 |
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#define TRAP_PER_CPU_DEV_MONDO_QMASK 0xec |
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#define TRAP_PER_CPU_RESUM_QMASK 0xf0 |
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#define TRAP_PER_CPU_NONRESUM_QMASK 0xf4 |
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#define TRAP_PER_CPU_PER_CPU_BASE 0xf8 |
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#define TRAP_BLOCK_SZ_SHIFT 8 |
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#include <asm/scratchpad.h> |
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#define __GET_CPUID(REG) \ |
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/* Spitfire implementation (default). */ \ |
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661: ldxa [%g0] ASI_UPA_CONFIG, REG; \ |
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srlx REG, 17, REG; \ |
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and REG, 0x1f, REG; \ |
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nop; \ |
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.section .cpuid_patch, "ax"; \ |
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/* Instruction location. */ \ |
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.word 661b; \ |
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/* Cheetah Safari implementation. */ \ |
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ldxa [%g0] ASI_SAFARI_CONFIG, REG; \ |
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srlx REG, 17, REG; \ |
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and REG, 0x3ff, REG; \ |
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nop; \ |
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/* Cheetah JBUS implementation. */ \ |
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ldxa [%g0] ASI_JBUS_CONFIG, REG; \ |
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srlx REG, 17, REG; \ |
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and REG, 0x1f, REG; \ |
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nop; \ |
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/* Starfire implementation. */ \ |
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sethi %hi(0x1fff40000d0 >> 9), REG; \ |
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sllx REG, 9, REG; \ |
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or REG, 0xd0, REG; \ |
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lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\ |
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/* sun4v implementation. */ \ |
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mov SCRATCHPAD_CPUID, REG; \ |
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ldxa [REG] ASI_SCRATCHPAD, REG; \ |
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nop; \ |
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nop; \ |
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.previous; |
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#ifdef CONFIG_SMP |
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#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
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__GET_CPUID(TMP) \ |
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sethi %hi(trap_block), DEST; \ |
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sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \ |
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or DEST, %lo(trap_block), DEST; \ |
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add DEST, TMP, DEST; \ |
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/* Clobbers TMP, current address space PGD phys address into DEST. */ |
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#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ |
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TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
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ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; |
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/* Clobbers TMP, loads local processor's IRQ work area into DEST. */ |
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#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \ |
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TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
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add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST; |
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/* Clobbers TMP, loads DEST with current thread info pointer. */ |
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#define TRAP_LOAD_THREAD_REG(DEST, TMP) \ |
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TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
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ldx [DEST + TRAP_PER_CPU_THREAD], DEST; |
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/* Given the current thread info pointer in THR, load the per-cpu |
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* area base of the current processor into DEST. REG1, REG2, and REG3 are |
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* clobbered. |
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* |
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* You absolutely cannot use DEST as a temporary in this code. The |
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* reason is that traps can happen during execution, and return from |
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* trap will load the fully resolved DEST per-cpu base. This can corrupt |
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* the calculations done by the macro mid-stream. |
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*/ |
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#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ |
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lduh [THR + TI_CPU], REG1; \ |
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sethi %hi(trap_block), REG2; \ |
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sllx REG1, TRAP_BLOCK_SZ_SHIFT, REG1; \ |
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or REG2, %lo(trap_block), REG2; \ |
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add REG2, REG1, REG2; \ |
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ldx [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST; |
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#else |
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#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
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sethi %hi(trap_block), DEST; \ |
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or DEST, %lo(trap_block), DEST; \ |
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/* Uniprocessor versions, we know the cpuid is zero. */ |
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#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ |
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TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
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ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; |
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/* Clobbers TMP, loads local processor's IRQ work area into DEST. */ |
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#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \ |
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TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
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add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST; |
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#define TRAP_LOAD_THREAD_REG(DEST, TMP) \ |
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TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ |
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ldx [DEST + TRAP_PER_CPU_THREAD], DEST; |
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/* No per-cpu areas on uniprocessor, so no need to load DEST. */ |
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#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) |
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#endif /* !(CONFIG_SMP) */ |
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#endif /* _SPARC_TRAP_BLOCK_H */
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