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192 lines
5.5 KiB
192 lines
5.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* ross.h: Ross module specific definitions and defines. |
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* |
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* Copyright (C) 1995 David S. Miller ([email protected]) |
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*/ |
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#ifndef _SPARC_ROSS_H |
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#define _SPARC_ROSS_H |
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#include <asm/asi.h> |
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#include <asm/page.h> |
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/* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers' |
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* field has '1111'. |
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*/ |
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/* The MMU control register fields on the HyperSparc. |
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* |
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* ----------------------------------------------------------------- |
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* |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME| |
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* ----------------------------------------------------------------- |
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* 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0 |
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* |
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* Phew, lots of fields there ;-) |
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* |
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* CWR: Cache Wrapping Enabled, if one cache wrapping is on. |
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* SE: Snoop Enable, turns on bus snooping for cache activity if one. |
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* WBE: Write Buffer Enable, one turns it on. |
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* MID: The ModuleID of the chip for MBus transactions. |
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* BM: Boot-Mode. One indicates the MMU is in boot mode. |
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* C: Indicates whether accesses are cachable while the MMU is |
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* disabled. |
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* CS: Cache Size -- 0 = 128k, 1 = 256k |
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* MR: Memory Reflection, one indicates that the memory bus connected |
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* to the MBus supports memory reflection. |
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* CM: Cache Mode -- 0 = write-through, 1 = copy-back |
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* CE: Cache Enable -- 0 = no caching, 1 = cache is on |
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* NF: No Fault -- 0 = faults trap the CPU from supervisor mode |
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* 1 = faults from supervisor mode do not generate traps |
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* ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on |
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*/ |
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#define HYPERSPARC_CWENABLE 0x00200000 |
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#define HYPERSPARC_SBENABLE 0x00100000 |
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#define HYPERSPARC_WBENABLE 0x00080000 |
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#define HYPERSPARC_MIDMASK 0x00078000 |
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#define HYPERSPARC_BMODE 0x00004000 |
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#define HYPERSPARC_ACENABLE 0x00002000 |
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#define HYPERSPARC_CSIZE 0x00001000 |
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#define HYPERSPARC_MRFLCT 0x00000800 |
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#define HYPERSPARC_CMODE 0x00000400 |
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#define HYPERSPARC_CENABLE 0x00000100 |
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#define HYPERSPARC_NFAULT 0x00000002 |
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#define HYPERSPARC_MENABLE 0x00000001 |
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/* The ICCR instruction cache register on the HyperSparc. |
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* |
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* ----------------------------------------------- |
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* | | FTD | ICE | |
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* ----------------------------------------------- |
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* 31 1 0 |
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* |
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* This register is accessed using the V8 'wrasr' and 'rdasr' |
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* opcodes, since not all assemblers understand them and those |
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* that do use different semantics I will just hard code the |
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* instruction with a '.word' statement. |
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* |
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* FTD: If set to one flush instructions executed during an |
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* instruction cache hit occurs, the corresponding line |
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* for said cache-hit is invalidated. If FTD is zero, |
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* an unimplemented 'flush' trap will occur when any |
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* flush is executed by the processor. |
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* |
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* ICE: If set to one, the instruction cache is enabled. If |
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* zero, the cache will not be used for instruction fetches. |
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* |
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* All other bits are read as zeros, and writes to them have no |
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* effect. |
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* |
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* Wheee, not many assemblers understand the %iccr register nor |
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* the generic asr r/w instructions. |
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* |
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* 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1 |
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* |
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* 0x 8 3 4 7 c 0 0 0 ! 0x8347c000 |
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* |
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* 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr |
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* |
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* 0x b f 8 0 6 0 0 0 ! 0xbf806000 |
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* |
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*/ |
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#define HYPERSPARC_ICCR_FTD 0x00000002 |
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#define HYPERSPARC_ICCR_ICE 0x00000001 |
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#ifndef __ASSEMBLY__ |
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static inline unsigned int get_ross_icr(void) |
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{ |
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unsigned int icreg; |
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__asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */ |
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"mov %%g1, %0\n\t" |
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: "=r" (icreg) |
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: /* no inputs */ |
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: "g1", "memory"); |
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return icreg; |
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} |
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static inline void put_ross_icr(unsigned int icreg) |
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{ |
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__asm__ __volatile__("or %%g0, %0, %%g1\n\t" |
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".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */ |
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"nop\n\t" |
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"nop\n\t" |
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"nop\n\t" |
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: /* no outputs */ |
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: "r" (icreg) |
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: "g1", "memory"); |
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return; |
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} |
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/* HyperSparc specific cache flushing. */ |
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/* This is for the on-chip instruction cache. */ |
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static inline void hyper_flush_whole_icache(void) |
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{ |
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__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" |
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: /* no outputs */ |
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: "i" (ASI_M_FLUSH_IWHOLE) |
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: "memory"); |
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return; |
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} |
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extern int vac_cache_size; |
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extern int vac_line_size; |
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static inline void hyper_clear_all_tags(void) |
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{ |
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unsigned long addr; |
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for(addr = 0; addr < vac_cache_size; addr += vac_line_size) |
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" |
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: /* no outputs */ |
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: "r" (addr), "i" (ASI_M_DATAC_TAG) |
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: "memory"); |
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} |
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static inline void hyper_flush_unconditional_combined(void) |
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{ |
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unsigned long addr; |
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for (addr = 0; addr < vac_cache_size; addr += vac_line_size) |
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" |
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: /* no outputs */ |
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: "r" (addr), "i" (ASI_M_FLUSH_CTX) |
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: "memory"); |
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} |
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static inline void hyper_flush_cache_user(void) |
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{ |
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unsigned long addr; |
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for (addr = 0; addr < vac_cache_size; addr += vac_line_size) |
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" |
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: /* no outputs */ |
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: "r" (addr), "i" (ASI_M_FLUSH_USER) |
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: "memory"); |
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} |
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static inline void hyper_flush_cache_page(unsigned long page) |
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{ |
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unsigned long end; |
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page &= PAGE_MASK; |
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end = page + PAGE_SIZE; |
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while (page < end) { |
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" |
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: /* no outputs */ |
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: "r" (page), "i" (ASI_M_FLUSH_PAGE) |
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: "memory"); |
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page += vac_line_size; |
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} |
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} |
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#endif /* !(__ASSEMBLY__) */ |
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#endif /* !(_SPARC_ROSS_H) */
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