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138 lines
4.3 KiB
138 lines
4.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* mxcc.h: Definitions of the Viking MXCC registers |
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* |
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* Copyright (C) 1995 David S. Miller ([email protected]) |
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*/ |
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#ifndef _SPARC_MXCC_H |
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#define _SPARC_MXCC_H |
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/* These registers are accessed through ASI 0x2. */ |
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#define MXCC_DATSTREAM 0x1C00000 /* Data stream register */ |
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#define MXCC_SRCSTREAM 0x1C00100 /* Source stream register */ |
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#define MXCC_DESSTREAM 0x1C00200 /* Destination stream register */ |
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#define MXCC_RMCOUNT 0x1C00300 /* Count of references and misses */ |
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#define MXCC_STEST 0x1C00804 /* Internal self-test */ |
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#define MXCC_CREG 0x1C00A04 /* Control register */ |
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#define MXCC_SREG 0x1C00B00 /* Status register */ |
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#define MXCC_RREG 0x1C00C04 /* Reset register */ |
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#define MXCC_EREG 0x1C00E00 /* Error code register */ |
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#define MXCC_PREG 0x1C00F04 /* Address port register */ |
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/* Some MXCC constants. */ |
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#define MXCC_STREAM_SIZE 0x20 /* Size in bytes of one stream r/w */ |
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/* The MXCC Control Register: |
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* |
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* ---------------------------------------------------------------------- |
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* | | RRC | RSV |PRE|MCE|PARE|ECE|RSV| |
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* ---------------------------------------------------------------------- |
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* 31 10 9 8-6 5 4 3 2 1-0 |
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* |
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* RRC: Controls what you read from MXCC_RMCOUNT reg. |
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* 0=Misses 1=References |
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* PRE: Prefetch enable |
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* MCE: Multiple Command Enable |
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* PARE: Parity enable |
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* ECE: External cache enable |
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*/ |
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#define MXCC_CTL_RRC 0x00000200 |
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#define MXCC_CTL_PRE 0x00000020 |
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#define MXCC_CTL_MCE 0x00000010 |
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#define MXCC_CTL_PARE 0x00000008 |
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#define MXCC_CTL_ECE 0x00000004 |
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/* The MXCC Error Register: |
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* |
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* -------------------------------------------------------- |
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* |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR| |
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* -------------------------------------------------------- |
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* 31 30 29 28 27 26 25 24-15 14-7 6 5-3 2-0 |
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* |
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* ME: Multiple Errors have occurred |
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* CE: Cache consistency Error |
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* PEW: Parity Error during a Write operation |
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* PEE: Parity Error involving the External cache |
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* ASE: ASynchronous Error |
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* EIV: This register is toast |
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* MOPC: MXCC Operation Code for instance causing error |
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* ECODE: The Error CODE |
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* PRIV: A privileged mode error? 0=no 1=yes |
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* HPADDR: High PhysicalADDRess bits (35-32) |
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*/ |
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#define MXCC_ERR_ME 0x80000000 |
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#define MXCC_ERR_CE 0x20000000 |
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#define MXCC_ERR_PEW 0x10000000 |
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#define MXCC_ERR_PEE 0x08000000 |
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#define MXCC_ERR_ASE 0x04000000 |
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#define MXCC_ERR_EIV 0x02000000 |
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#define MXCC_ERR_MOPC 0x01FF8000 |
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#define MXCC_ERR_ECODE 0x00007F80 |
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#define MXCC_ERR_PRIV 0x00000040 |
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#define MXCC_ERR_HPADDR 0x0000000f |
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/* The MXCC Port register: |
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* |
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* ----------------------------------------------------- |
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* | | MID | | |
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* ----------------------------------------------------- |
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* 31 21 20-18 17 0 |
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* |
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* MID: The moduleID of the cpu your read this from. |
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*/ |
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#ifndef __ASSEMBLY__ |
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static inline void mxcc_set_stream_src(unsigned long *paddr) |
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{ |
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unsigned long data0 = paddr[0]; |
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unsigned long data1 = paddr[1]; |
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__asm__ __volatile__ ("or %%g0, %0, %%g2\n\t" |
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"or %%g0, %1, %%g3\n\t" |
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"stda %%g2, [%2] %3\n\t" : : |
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"r" (data0), "r" (data1), |
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"r" (MXCC_SRCSTREAM), |
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"i" (ASI_M_MXCC) : "g2", "g3"); |
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} |
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static inline void mxcc_set_stream_dst(unsigned long *paddr) |
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{ |
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unsigned long data0 = paddr[0]; |
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unsigned long data1 = paddr[1]; |
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__asm__ __volatile__ ("or %%g0, %0, %%g2\n\t" |
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"or %%g0, %1, %%g3\n\t" |
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"stda %%g2, [%2] %3\n\t" : : |
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"r" (data0), "r" (data1), |
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"r" (MXCC_DESSTREAM), |
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"i" (ASI_M_MXCC) : "g2", "g3"); |
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} |
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static inline unsigned long mxcc_get_creg(void) |
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{ |
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unsigned long mxcc_control; |
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__asm__ __volatile__("set 0xffffffff, %%g2\n\t" |
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"set 0xffffffff, %%g3\n\t" |
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"stda %%g2, [%1] %2\n\t" |
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"lda [%3] %2, %0\n\t" : |
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"=r" (mxcc_control) : |
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"r" (MXCC_EREG), "i" (ASI_M_MXCC), |
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"r" (MXCC_CREG) : "g2", "g3"); |
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return mxcc_control; |
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} |
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static inline void mxcc_set_creg(unsigned long mxcc_control) |
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{ |
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__asm__ __volatile__("sta %0, [%1] %2\n\t" : : |
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"r" (mxcc_control), "r" (MXCC_CREG), |
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"i" (ASI_M_MXCC)); |
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} |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* !(_SPARC_MXCC_H) */
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