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123 lines
4.3 KiB
123 lines
4.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* ecc.h: Definitions and defines for the external cache/memory |
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* controller on the sun4m. |
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* |
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* Copyright (C) 1995 David S. Miller ([email protected]) |
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*/ |
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#ifndef _SPARC_ECC_H |
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#define _SPARC_ECC_H |
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/* These registers are accessed through the SRMMU passthrough ASI 0x20 */ |
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#define ECC_ENABLE 0x00000000 /* ECC enable register */ |
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#define ECC_FSTATUS 0x00000008 /* ECC fault status register */ |
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#define ECC_FADDR 0x00000010 /* ECC fault address register */ |
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#define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */ |
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#define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */ |
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#define ECC_DMESG 0x00001000 /* Diagnostic message passing area */ |
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/* ECC MBus Arbiter Enable register: |
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* |
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* ---------------------------------------- |
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* | |SBUS|MOD3|MOD2|MOD1|RSV| |
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* ---------------------------------------- |
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* 31 5 4 3 2 1 0 |
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* |
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* SBUS: Enable MBus Arbiter on the SBus 0=off 1=on |
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* MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on |
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* MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on |
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* MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on |
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*/ |
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#define ECC_MBAE_SBUS 0x00000010 |
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#define ECC_MBAE_MOD3 0x00000008 |
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#define ECC_MBAE_MOD2 0x00000004 |
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#define ECC_MBAE_MOD1 0x00000002 |
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/* ECC Fault Control Register layout: |
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* |
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* ----------------------------- |
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* | RESV | ECHECK | EINT | |
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* ----------------------------- |
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* 31 2 1 0 |
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* |
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* ECHECK: Enable ECC checking. 0=off 1=on |
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* EINT: Enable Interrupts for correctable errors. 0=off 1=on |
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*/ |
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#define ECC_FCR_CHECK 0x00000002 |
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#define ECC_FCR_INTENAB 0x00000001 |
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/* ECC Fault Address Register Zero layout: |
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* |
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* ----------------------------------------------------- |
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* | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR | |
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* ----------------------------------------------------- |
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* 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0 |
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* |
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* MID: ModuleID of the faulting processor. ie. who did it? |
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* S: Supervisor/Privileged access? 0=no 1=yes |
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* VA: Bits 19-12 of the virtual faulting address, these are the |
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* superset bits in the virtual cache and can be used for |
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* a flush operation if necessary. |
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* BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot |
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* mode bit. |
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* AT: Did this fault happen during an atomic instruction? 0=no |
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* 1=yes. This means either an 'ldstub' or 'swap' instruction |
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* was in progress (but not finished) when this fault happened. |
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* This indicated whether the bus was locked when the fault |
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* occurred. |
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* C: Did the pte for this access indicate that it was cacheable? |
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* 0=no 1=yes |
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* SZ: The size of the transaction. |
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* TYP: The transaction type. |
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* PADDR: Bits 35-32 of the physical address for the fault. |
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*/ |
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#define ECC_FADDR0_MIDMASK 0xf0000000 |
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#define ECC_FADDR0_S 0x08000000 |
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#define ECC_FADDR0_VADDR 0x003fc000 |
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#define ECC_FADDR0_BMODE 0x00002000 |
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#define ECC_FADDR0_ATOMIC 0x00001000 |
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#define ECC_FADDR0_CACHE 0x00000800 |
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#define ECC_FADDR0_SIZE 0x00000700 |
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#define ECC_FADDR0_TYPE 0x000000f0 |
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#define ECC_FADDR0_PADDR 0x0000000f |
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/* ECC Fault Address Register One layout: |
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* |
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* ------------------------------------- |
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* | Physical Address 31-0 | |
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* ------------------------------------- |
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* 31 0 |
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* |
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* You get the upper 4 bits of the physical address from the |
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* PADDR field in ECC Fault Address Zero register. |
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*/ |
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/* ECC Fault Status Register layout: |
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* |
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* ---------------------------------------------- |
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* | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C| |
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* ---------------------------------------------- |
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* 31-18 17 16 15-8 7-4 3 2 1 0 |
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* |
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* C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only) |
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* MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes) |
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* SYNDROME: Controller is mentally unstable. |
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* DWORD: |
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* UNC: Uncorrectable error. 0=no 1=yes |
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* TIMEO: Timeout occurred. 0=no 1=yes |
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* BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only) |
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* C: Correctable error? 0=no 1=yes |
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*/ |
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#define ECC_FSR_C2ERR 0x00020000 |
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#define ECC_FSR_MULT 0x00010000 |
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#define ECC_FSR_SYND 0x0000ff00 |
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#define ECC_FSR_DWORD 0x000000f0 |
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#define ECC_FSR_UNC 0x00000008 |
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#define ECC_FSR_TIMEO 0x00000004 |
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#define ECC_FSR_BADSLOT 0x00000002 |
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#define ECC_FSR_C 0x00000001 |
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#endif /* !(_SPARC_ECC_H) */
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