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396 lines
12 KiB
396 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* SH-X3 Prototype Setup |
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* |
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* Copyright (C) 2007 - 2010 Paul Mundt |
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*/ |
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#include <linux/platform_device.h> |
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#include <linux/init.h> |
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#include <linux/serial.h> |
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#include <linux/serial_sci.h> |
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#include <linux/io.h> |
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#include <linux/gpio.h> |
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#include <linux/sh_timer.h> |
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#include <linux/sh_intc.h> |
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#include <cpu/shx3.h> |
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#include <asm/mmzone.h> |
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#include <asm/platform_early.h> |
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/* |
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* This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2 |
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* INTEVT values overlap with the FPU EXPEVT ones, requiring special |
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* demuxing in the exception dispatch path. |
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* |
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* As this overlap is something that never should have made it in to |
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* silicon in the first place, we just refuse to deal with the port at |
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* all rather than adding infrastructure to hack around it. |
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*/ |
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static struct plat_sci_port scif0_platform_data = { |
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.scscr = SCSCR_REIE, |
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.type = PORT_SCIF, |
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}; |
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static struct resource scif0_resources[] = { |
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DEFINE_RES_MEM(0xffc30000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0x700)), |
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DEFINE_RES_IRQ(evt2irq(0x720)), |
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DEFINE_RES_IRQ(evt2irq(0x760)), |
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DEFINE_RES_IRQ(evt2irq(0x740)), |
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}; |
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static struct platform_device scif0_device = { |
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.name = "sh-sci", |
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.id = 0, |
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.resource = scif0_resources, |
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.num_resources = ARRAY_SIZE(scif0_resources), |
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.dev = { |
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.platform_data = &scif0_platform_data, |
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}, |
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}; |
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static struct plat_sci_port scif1_platform_data = { |
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.scscr = SCSCR_REIE, |
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.type = PORT_SCIF, |
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}; |
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static struct resource scif1_resources[] = { |
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DEFINE_RES_MEM(0xffc40000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0x780)), |
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DEFINE_RES_IRQ(evt2irq(0x7a0)), |
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DEFINE_RES_IRQ(evt2irq(0x7e0)), |
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DEFINE_RES_IRQ(evt2irq(0x7c0)), |
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}; |
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static struct platform_device scif1_device = { |
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.name = "sh-sci", |
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.id = 1, |
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.resource = scif1_resources, |
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.num_resources = ARRAY_SIZE(scif1_resources), |
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.dev = { |
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.platform_data = &scif1_platform_data, |
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}, |
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}; |
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static struct plat_sci_port scif2_platform_data = { |
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.scscr = SCSCR_REIE, |
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.type = PORT_SCIF, |
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}; |
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static struct resource scif2_resources[] = { |
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DEFINE_RES_MEM(0xffc60000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0x880)), |
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DEFINE_RES_IRQ(evt2irq(0x8a0)), |
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DEFINE_RES_IRQ(evt2irq(0x8e0)), |
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DEFINE_RES_IRQ(evt2irq(0x8c0)), |
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}; |
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static struct platform_device scif2_device = { |
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.name = "sh-sci", |
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.id = 2, |
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.resource = scif2_resources, |
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.num_resources = ARRAY_SIZE(scif2_resources), |
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.dev = { |
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.platform_data = &scif2_platform_data, |
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}, |
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}; |
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static struct sh_timer_config tmu0_platform_data = { |
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.channels_mask = 7, |
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}; |
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static struct resource tmu0_resources[] = { |
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DEFINE_RES_MEM(0xffc10000, 0x30), |
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DEFINE_RES_IRQ(evt2irq(0x400)), |
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DEFINE_RES_IRQ(evt2irq(0x420)), |
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DEFINE_RES_IRQ(evt2irq(0x440)), |
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}; |
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static struct platform_device tmu0_device = { |
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.name = "sh-tmu", |
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.id = 0, |
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.dev = { |
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.platform_data = &tmu0_platform_data, |
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}, |
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.resource = tmu0_resources, |
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.num_resources = ARRAY_SIZE(tmu0_resources), |
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}; |
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static struct sh_timer_config tmu1_platform_data = { |
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.channels_mask = 7, |
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}; |
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static struct resource tmu1_resources[] = { |
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DEFINE_RES_MEM(0xffc20000, 0x2c), |
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DEFINE_RES_IRQ(evt2irq(0x460)), |
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DEFINE_RES_IRQ(evt2irq(0x480)), |
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DEFINE_RES_IRQ(evt2irq(0x4a0)), |
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}; |
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static struct platform_device tmu1_device = { |
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.name = "sh-tmu", |
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.id = 1, |
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.dev = { |
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.platform_data = &tmu1_platform_data, |
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}, |
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.resource = tmu1_resources, |
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.num_resources = ARRAY_SIZE(tmu1_resources), |
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}; |
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static struct platform_device *shx3_early_devices[] __initdata = { |
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&scif0_device, |
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&scif1_device, |
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&scif2_device, |
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&tmu0_device, |
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&tmu1_device, |
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}; |
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static int __init shx3_devices_setup(void) |
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{ |
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return platform_add_devices(shx3_early_devices, |
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ARRAY_SIZE(shx3_early_devices)); |
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} |
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arch_initcall(shx3_devices_setup); |
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void __init plat_early_device_setup(void) |
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{ |
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sh_early_platform_add_devices(shx3_early_devices, |
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ARRAY_SIZE(shx3_early_devices)); |
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} |
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enum { |
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UNUSED = 0, |
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|
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/* interrupt sources */ |
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IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, |
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IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, |
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IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, |
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IRL_HHLL, IRL_HHLH, IRL_HHHL, |
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IRQ0, IRQ1, IRQ2, IRQ3, |
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HUDII, |
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TMU0, TMU1, TMU2, TMU3, TMU4, TMU5, |
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PCII0, PCII1, PCII2, PCII3, PCII4, |
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PCII5, PCII6, PCII7, PCII8, PCII9, |
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, |
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, |
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, |
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SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI, |
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DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, |
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DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE, |
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DU, |
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DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9, |
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DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE, |
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IIC, VIN0, VIN1, VCORE0, ATAPI, |
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DTU0, DTU1, DTU2, DTU3, |
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FE0, FE1, |
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GPIO0, GPIO1, GPIO2, GPIO3, |
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PAM, IRM, |
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INTICI0, INTICI1, INTICI2, INTICI3, |
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INTICI4, INTICI5, INTICI6, INTICI7, |
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/* interrupt groups */ |
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IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, |
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DMAC0, DMAC1, |
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}; |
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static struct intc_vect vectors[] __initdata = { |
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INTC_VECT(HUDII, 0x3e0), |
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
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INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460), |
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INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0), |
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INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520), |
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INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560), |
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INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0), |
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INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0), |
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INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620), |
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INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), |
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INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), |
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INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), |
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INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), |
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INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0), |
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INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0), |
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INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920), |
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INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960), |
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INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0), |
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INTC_VECT(DMAC0_DMAE, 0x9c0), |
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INTC_VECT(DU, 0x9e0), |
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INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20), |
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INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60), |
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INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0), |
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INTC_VECT(DMAC1_DMAE, 0xac0), |
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INTC_VECT(IIC, 0xae0), |
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INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20), |
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INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60), |
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INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20), |
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INTC_VECT(DTU0, 0xc40), |
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INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80), |
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INTC_VECT(DTU1, 0xca0), |
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INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0), |
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INTC_VECT(DTU2, 0xd00), |
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INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40), |
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INTC_VECT(DTU3, 0xd60), |
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INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20), |
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INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60), |
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INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0), |
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INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0), |
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INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20), |
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INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60), |
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INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0), |
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INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), |
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}; |
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static struct intc_group groups[] __initdata = { |
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INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, |
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IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, |
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IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, |
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IRL_HHLL, IRL_HHLH, IRL_HHHL), |
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INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9), |
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), |
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), |
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INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI), |
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INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, |
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DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), |
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INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, |
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DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), |
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}; |
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#define INT2DISTCR0 0xfe4108a0 |
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#define INT2DISTCR1 0xfe4108a4 |
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#define INT2DISTCR2 0xfe4108a8 |
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static struct intc_mask_reg mask_registers[] __initdata = { |
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{ 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ |
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{ IRQ0, IRQ1, IRQ2, IRQ3 } }, |
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{ 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */ |
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{ IRL } }, |
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{ 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */ |
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{ FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC, |
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DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0, |
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0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */ |
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0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, }, |
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INTC_SMP_BALANCING(INT2DISTCR0) }, |
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{ 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */ |
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{ 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */ |
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PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2, |
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PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11, |
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DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7, |
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DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4, |
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DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 }, |
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INTC_SMP_BALANCING(INT2DISTCR1) }, |
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{ 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */ |
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI, |
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SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI, |
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SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI, |
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SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI }, |
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INTC_SMP_BALANCING(INT2DISTCR2) }, |
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}; |
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static struct intc_prio_reg prio_registers[] __initdata = { |
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{ 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, |
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{ 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4, |
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TMU3, TMU2, TMU1, TMU0 } }, |
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{ 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0, |
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SCIF3, SCIF2, |
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SCIF1, SCIF0 } }, |
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{ 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, |
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PCII56789, PCII4, |
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PCII3, PCII2, |
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PCII1, PCII0 } }, |
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{ 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0, |
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VIN1, VIN0, IIC, DU} }, |
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{ 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3, |
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GPIO2, GPIO1, GPIO0, IRM } }, |
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{ 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */ |
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{ INTICI7, INTICI6, INTICI5, INTICI4, |
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INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) }, |
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}; |
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static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, |
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mask_registers, prio_registers, NULL); |
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/* Support for external interrupt pins in IRQ mode */ |
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static struct intc_vect vectors_irq[] __initdata = { |
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INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), |
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INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), |
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}; |
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static struct intc_sense_reg sense_registers[] __initdata = { |
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{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, |
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}; |
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static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups, |
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mask_registers, prio_registers, sense_registers); |
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/* External interrupt pins in IRL mode */ |
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static struct intc_vect vectors_irl[] __initdata = { |
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INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), |
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INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), |
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INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), |
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INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), |
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INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), |
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INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), |
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INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), |
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INTC_VECT(IRL_HHHL, 0x3c0), |
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}; |
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static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups, |
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mask_registers, prio_registers, NULL); |
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|
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void __init plat_irq_setup_pins(int mode) |
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{ |
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int ret = 0; |
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|
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switch (mode) { |
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case IRQ_MODE_IRQ: |
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ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name); |
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ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name); |
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ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name); |
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ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name); |
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if (unlikely(ret)) { |
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pr_err("Failed to set IRQ mode\n"); |
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return; |
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} |
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register_intc_controller(&intc_desc_irq); |
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break; |
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case IRQ_MODE_IRL3210: |
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ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name); |
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ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name); |
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ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name); |
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ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name); |
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if (unlikely(ret)) { |
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pr_err("Failed to set IRL mode\n"); |
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return; |
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} |
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register_intc_controller(&intc_desc_irl); |
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break; |
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default: |
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BUG(); |
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} |
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} |
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void __init plat_irq_setup(void) |
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{ |
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register_intc_controller(&intc_desc); |
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} |
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|
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void __init plat_mem_setup(void) |
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{ |
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unsigned int nid = 1; |
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|
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/* Register CPU#0 URAM space as Node 1 */ |
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setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */ |
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#if 0 |
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/* XXX: Not yet.. */ |
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setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */ |
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setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */ |
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setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */ |
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#endif |
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setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */ |
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}
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