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644 lines
16 KiB
644 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* SH7723 Setup |
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* |
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* Copyright (C) 2008 Paul Mundt |
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*/ |
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#include <linux/platform_device.h> |
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#include <linux/init.h> |
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#include <linux/serial.h> |
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#include <linux/mm.h> |
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#include <linux/serial_sci.h> |
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#include <linux/uio_driver.h> |
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#include <linux/usb/r8a66597.h> |
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#include <linux/sh_timer.h> |
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#include <linux/sh_intc.h> |
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#include <linux/io.h> |
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#include <asm/clock.h> |
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#include <asm/mmzone.h> |
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#include <asm/platform_early.h> |
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#include <cpu/sh7723.h> |
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/* Serial */ |
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static struct plat_sci_port scif0_platform_data = { |
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.scscr = SCSCR_REIE, |
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.type = PORT_SCIF, |
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.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
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}; |
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static struct resource scif0_resources[] = { |
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DEFINE_RES_MEM(0xffe00000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0xc00)), |
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}; |
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static struct platform_device scif0_device = { |
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.name = "sh-sci", |
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.id = 0, |
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.resource = scif0_resources, |
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.num_resources = ARRAY_SIZE(scif0_resources), |
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.dev = { |
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.platform_data = &scif0_platform_data, |
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}, |
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}; |
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static struct plat_sci_port scif1_platform_data = { |
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.scscr = SCSCR_REIE, |
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.type = PORT_SCIF, |
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.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
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}; |
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static struct resource scif1_resources[] = { |
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DEFINE_RES_MEM(0xffe10000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0xc20)), |
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}; |
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static struct platform_device scif1_device = { |
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.name = "sh-sci", |
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.id = 1, |
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.resource = scif1_resources, |
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.num_resources = ARRAY_SIZE(scif1_resources), |
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.dev = { |
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.platform_data = &scif1_platform_data, |
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}, |
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}; |
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static struct plat_sci_port scif2_platform_data = { |
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.scscr = SCSCR_REIE, |
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.type = PORT_SCIF, |
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.regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
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}; |
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static struct resource scif2_resources[] = { |
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DEFINE_RES_MEM(0xffe20000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0xc40)), |
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}; |
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static struct platform_device scif2_device = { |
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.name = "sh-sci", |
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.id = 2, |
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.resource = scif2_resources, |
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.num_resources = ARRAY_SIZE(scif2_resources), |
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.dev = { |
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.platform_data = &scif2_platform_data, |
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}, |
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}; |
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static struct plat_sci_port scif3_platform_data = { |
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.sampling_rate = 8, |
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.type = PORT_SCIFA, |
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}; |
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static struct resource scif3_resources[] = { |
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DEFINE_RES_MEM(0xa4e30000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0x900)), |
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}; |
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static struct platform_device scif3_device = { |
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.name = "sh-sci", |
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.id = 3, |
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.resource = scif3_resources, |
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.num_resources = ARRAY_SIZE(scif3_resources), |
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.dev = { |
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.platform_data = &scif3_platform_data, |
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}, |
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}; |
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static struct plat_sci_port scif4_platform_data = { |
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.sampling_rate = 8, |
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.type = PORT_SCIFA, |
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}; |
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static struct resource scif4_resources[] = { |
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DEFINE_RES_MEM(0xa4e40000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0xd00)), |
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}; |
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static struct platform_device scif4_device = { |
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.name = "sh-sci", |
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.id = 4, |
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.resource = scif4_resources, |
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.num_resources = ARRAY_SIZE(scif4_resources), |
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.dev = { |
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.platform_data = &scif4_platform_data, |
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}, |
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}; |
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static struct plat_sci_port scif5_platform_data = { |
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.sampling_rate = 8, |
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.type = PORT_SCIFA, |
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}; |
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static struct resource scif5_resources[] = { |
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DEFINE_RES_MEM(0xa4e50000, 0x100), |
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DEFINE_RES_IRQ(evt2irq(0xfa0)), |
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}; |
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static struct platform_device scif5_device = { |
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.name = "sh-sci", |
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.id = 5, |
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.resource = scif5_resources, |
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.num_resources = ARRAY_SIZE(scif5_resources), |
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.dev = { |
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.platform_data = &scif5_platform_data, |
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}, |
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}; |
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static struct uio_info vpu_platform_data = { |
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.name = "VPU5", |
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.version = "0", |
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.irq = evt2irq(0x980), |
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}; |
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static struct resource vpu_resources[] = { |
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[0] = { |
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.name = "VPU", |
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.start = 0xfe900000, |
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.end = 0xfe902807, |
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.flags = IORESOURCE_MEM, |
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}, |
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[1] = { |
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/* place holder for contiguous memory */ |
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}, |
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}; |
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static struct platform_device vpu_device = { |
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.name = "uio_pdrv_genirq", |
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.id = 0, |
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.dev = { |
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.platform_data = &vpu_platform_data, |
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}, |
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.resource = vpu_resources, |
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.num_resources = ARRAY_SIZE(vpu_resources), |
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}; |
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static struct uio_info veu0_platform_data = { |
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.name = "VEU2H", |
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.version = "0", |
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.irq = evt2irq(0x8c0), |
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}; |
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static struct resource veu0_resources[] = { |
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[0] = { |
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.name = "VEU2H0", |
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.start = 0xfe920000, |
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.end = 0xfe92027b, |
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.flags = IORESOURCE_MEM, |
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}, |
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[1] = { |
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/* place holder for contiguous memory */ |
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}, |
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}; |
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static struct platform_device veu0_device = { |
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.name = "uio_pdrv_genirq", |
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.id = 1, |
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.dev = { |
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.platform_data = &veu0_platform_data, |
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}, |
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.resource = veu0_resources, |
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.num_resources = ARRAY_SIZE(veu0_resources), |
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}; |
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static struct uio_info veu1_platform_data = { |
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.name = "VEU2H", |
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.version = "0", |
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.irq = evt2irq(0x560), |
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}; |
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static struct resource veu1_resources[] = { |
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[0] = { |
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.name = "VEU2H1", |
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.start = 0xfe924000, |
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.end = 0xfe92427b, |
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.flags = IORESOURCE_MEM, |
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}, |
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[1] = { |
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/* place holder for contiguous memory */ |
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}, |
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}; |
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static struct platform_device veu1_device = { |
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.name = "uio_pdrv_genirq", |
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.id = 2, |
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.dev = { |
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.platform_data = &veu1_platform_data, |
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}, |
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.resource = veu1_resources, |
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.num_resources = ARRAY_SIZE(veu1_resources), |
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}; |
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static struct sh_timer_config cmt_platform_data = { |
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.channels_mask = 0x20, |
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}; |
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static struct resource cmt_resources[] = { |
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DEFINE_RES_MEM(0x044a0000, 0x70), |
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DEFINE_RES_IRQ(evt2irq(0xf00)), |
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}; |
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static struct platform_device cmt_device = { |
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.name = "sh-cmt-32", |
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.id = 0, |
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.dev = { |
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.platform_data = &cmt_platform_data, |
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}, |
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.resource = cmt_resources, |
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.num_resources = ARRAY_SIZE(cmt_resources), |
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}; |
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static struct sh_timer_config tmu0_platform_data = { |
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.channels_mask = 7, |
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}; |
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static struct resource tmu0_resources[] = { |
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DEFINE_RES_MEM(0xffd80000, 0x2c), |
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DEFINE_RES_IRQ(evt2irq(0x400)), |
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DEFINE_RES_IRQ(evt2irq(0x420)), |
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DEFINE_RES_IRQ(evt2irq(0x440)), |
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}; |
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static struct platform_device tmu0_device = { |
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.name = "sh-tmu", |
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.id = 0, |
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.dev = { |
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.platform_data = &tmu0_platform_data, |
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}, |
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.resource = tmu0_resources, |
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.num_resources = ARRAY_SIZE(tmu0_resources), |
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}; |
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static struct sh_timer_config tmu1_platform_data = { |
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.channels_mask = 7, |
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}; |
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static struct resource tmu1_resources[] = { |
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DEFINE_RES_MEM(0xffd90000, 0x2c), |
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DEFINE_RES_IRQ(evt2irq(0x920)), |
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DEFINE_RES_IRQ(evt2irq(0x940)), |
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DEFINE_RES_IRQ(evt2irq(0x960)), |
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}; |
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static struct platform_device tmu1_device = { |
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.name = "sh-tmu", |
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.id = 1, |
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.dev = { |
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.platform_data = &tmu1_platform_data, |
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}, |
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.resource = tmu1_resources, |
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.num_resources = ARRAY_SIZE(tmu1_resources), |
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}; |
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static struct resource rtc_resources[] = { |
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[0] = { |
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.start = 0xa465fec0, |
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.end = 0xa465fec0 + 0x58 - 1, |
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.flags = IORESOURCE_IO, |
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}, |
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[1] = { |
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/* Period IRQ */ |
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.start = evt2irq(0xaa0), |
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.flags = IORESOURCE_IRQ, |
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}, |
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[2] = { |
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/* Carry IRQ */ |
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.start = evt2irq(0xac0), |
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.flags = IORESOURCE_IRQ, |
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}, |
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[3] = { |
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/* Alarm IRQ */ |
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.start = evt2irq(0xa80), |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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static struct platform_device rtc_device = { |
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.name = "sh-rtc", |
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.id = -1, |
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.num_resources = ARRAY_SIZE(rtc_resources), |
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.resource = rtc_resources, |
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}; |
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static struct r8a66597_platdata r8a66597_data = { |
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.on_chip = 1, |
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}; |
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static struct resource sh7723_usb_host_resources[] = { |
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[0] = { |
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.start = 0xa4d80000, |
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.end = 0xa4d800ff, |
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.flags = IORESOURCE_MEM, |
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}, |
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[1] = { |
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.start = evt2irq(0xa20), |
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.end = evt2irq(0xa20), |
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.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, |
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}, |
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}; |
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static struct platform_device sh7723_usb_host_device = { |
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.name = "r8a66597_hcd", |
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.id = 0, |
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.dev = { |
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.dma_mask = NULL, /* not use dma */ |
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.coherent_dma_mask = 0xffffffff, |
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.platform_data = &r8a66597_data, |
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}, |
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.num_resources = ARRAY_SIZE(sh7723_usb_host_resources), |
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.resource = sh7723_usb_host_resources, |
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}; |
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static struct resource iic_resources[] = { |
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[0] = { |
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.name = "IIC", |
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.start = 0x04470000, |
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.end = 0x04470017, |
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.flags = IORESOURCE_MEM, |
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}, |
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[1] = { |
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.start = evt2irq(0xe00), |
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.end = evt2irq(0xe60), |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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static struct platform_device iic_device = { |
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.name = "i2c-sh_mobile", |
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.id = 0, /* "i2c0" clock */ |
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.num_resources = ARRAY_SIZE(iic_resources), |
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.resource = iic_resources, |
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}; |
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static struct platform_device *sh7723_devices[] __initdata = { |
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&scif0_device, |
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&scif1_device, |
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&scif2_device, |
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&scif3_device, |
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&scif4_device, |
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&scif5_device, |
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&cmt_device, |
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&tmu0_device, |
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&tmu1_device, |
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&rtc_device, |
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&iic_device, |
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&sh7723_usb_host_device, |
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&vpu_device, |
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&veu0_device, |
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&veu1_device, |
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}; |
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static int __init sh7723_devices_setup(void) |
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{ |
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platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); |
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platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); |
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platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); |
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return platform_add_devices(sh7723_devices, |
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ARRAY_SIZE(sh7723_devices)); |
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} |
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arch_initcall(sh7723_devices_setup); |
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static struct platform_device *sh7723_early_devices[] __initdata = { |
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&scif0_device, |
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&scif1_device, |
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&scif2_device, |
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&scif3_device, |
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&scif4_device, |
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&scif5_device, |
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&cmt_device, |
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&tmu0_device, |
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&tmu1_device, |
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}; |
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void __init plat_early_device_setup(void) |
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{ |
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sh_early_platform_add_devices(sh7723_early_devices, |
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ARRAY_SIZE(sh7723_early_devices)); |
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} |
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#define RAMCR_CACHE_L2FC 0x0002 |
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#define RAMCR_CACHE_L2E 0x0001 |
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#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) |
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void l2_cache_init(void) |
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{ |
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/* Enable L2 cache */ |
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__raw_writel(L2_CACHE_ENABLE, RAMCR); |
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} |
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enum { |
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UNUSED=0, |
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ENABLED, |
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DISABLED, |
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/* interrupt sources */ |
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, |
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HUDI, |
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DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, |
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_2DG_TRI,_2DG_INI,_2DG_CEI, |
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DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, |
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VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, |
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SCIFA_SCIFA0, |
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VPU_VPUI, |
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TPU_TPUI, |
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ADC_ADI, |
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USB_USI0, |
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RTC_ATI,RTC_PRI,RTC_CUI, |
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DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, |
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DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, |
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KEYSC_KEYI, |
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SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, |
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MSIOF_MSIOFI0,MSIOF_MSIOFI1, |
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SCIFA_SCIFA1, |
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FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, |
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I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, |
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CMT_CMTI, |
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TSIF_TSIFI, |
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SIU_SIUI, |
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SCIFA_SCIFA2, |
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TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, |
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IRDA_IRDAI, |
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ATAPI_ATAPII, |
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VEU2H1_VEU2HI, |
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LCDC_LCDCI, |
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TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, |
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/* interrupt groups */ |
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DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, |
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SDHI1, RTC, DMAC1B, SDHI0, |
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}; |
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static struct intc_vect vectors[] __initdata = { |
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), |
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), |
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INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), |
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INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), |
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INTC_VECT(DMAC1A_DEI0,0x700), |
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INTC_VECT(DMAC1A_DEI1,0x720), |
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INTC_VECT(DMAC1A_DEI2,0x740), |
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INTC_VECT(DMAC1A_DEI3,0x760), |
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INTC_VECT(_2DG_TRI, 0x780), |
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INTC_VECT(_2DG_INI, 0x7A0), |
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INTC_VECT(_2DG_CEI, 0x7C0), |
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INTC_VECT(DMAC0A_DEI0,0x800), |
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INTC_VECT(DMAC0A_DEI1,0x820), |
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INTC_VECT(DMAC0A_DEI2,0x840), |
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INTC_VECT(DMAC0A_DEI3,0x860), |
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INTC_VECT(VIO_CEUI,0x880), |
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INTC_VECT(VIO_BEUI,0x8A0), |
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INTC_VECT(VIO_VEU2HI,0x8C0), |
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INTC_VECT(VIO_VOUI,0x8E0), |
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INTC_VECT(SCIFA_SCIFA0,0x900), |
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INTC_VECT(VPU_VPUI,0x980), |
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INTC_VECT(TPU_TPUI,0x9A0), |
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INTC_VECT(ADC_ADI,0x9E0), |
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INTC_VECT(USB_USI0,0xA20), |
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INTC_VECT(RTC_ATI,0xA80), |
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INTC_VECT(RTC_PRI,0xAA0), |
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INTC_VECT(RTC_CUI,0xAC0), |
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INTC_VECT(DMAC1B_DEI4,0xB00), |
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INTC_VECT(DMAC1B_DEI5,0xB20), |
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INTC_VECT(DMAC1B_DADERR,0xB40), |
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INTC_VECT(DMAC0B_DEI4,0xB80), |
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INTC_VECT(DMAC0B_DEI5,0xBA0), |
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INTC_VECT(DMAC0B_DADERR,0xBC0), |
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INTC_VECT(KEYSC_KEYI,0xBE0), |
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INTC_VECT(SCIF_SCIF0,0xC00), |
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INTC_VECT(SCIF_SCIF1,0xC20), |
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INTC_VECT(SCIF_SCIF2,0xC40), |
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INTC_VECT(MSIOF_MSIOFI0,0xC80), |
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INTC_VECT(MSIOF_MSIOFI1,0xCA0), |
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INTC_VECT(SCIFA_SCIFA1,0xD00), |
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INTC_VECT(FLCTL_FLSTEI,0xD80), |
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INTC_VECT(FLCTL_FLTENDI,0xDA0), |
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INTC_VECT(FLCTL_FLTREQ0I,0xDC0), |
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INTC_VECT(FLCTL_FLTREQ1I,0xDE0), |
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INTC_VECT(I2C_ALI,0xE00), |
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INTC_VECT(I2C_TACKI,0xE20), |
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INTC_VECT(I2C_WAITI,0xE40), |
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INTC_VECT(I2C_DTEI,0xE60), |
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INTC_VECT(SDHI0, 0xE80), |
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INTC_VECT(SDHI0, 0xEA0), |
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INTC_VECT(SDHI0, 0xEC0), |
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INTC_VECT(CMT_CMTI,0xF00), |
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INTC_VECT(TSIF_TSIFI,0xF20), |
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INTC_VECT(SIU_SIUI,0xF80), |
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INTC_VECT(SCIFA_SCIFA2,0xFA0), |
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INTC_VECT(TMU0_TUNI0,0x400), |
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INTC_VECT(TMU0_TUNI1,0x420), |
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INTC_VECT(TMU0_TUNI2,0x440), |
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|
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INTC_VECT(IRDA_IRDAI,0x480), |
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INTC_VECT(ATAPI_ATAPII,0x4A0), |
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|
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INTC_VECT(SDHI1, 0x4E0), |
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INTC_VECT(SDHI1, 0x500), |
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INTC_VECT(SDHI1, 0x520), |
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|
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INTC_VECT(VEU2H1_VEU2HI,0x560), |
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INTC_VECT(LCDC_LCDCI,0x580), |
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|
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INTC_VECT(TMU1_TUNI0,0x920), |
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INTC_VECT(TMU1_TUNI1,0x940), |
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INTC_VECT(TMU1_TUNI2,0x960), |
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|
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}; |
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|
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static struct intc_group groups[] __initdata = { |
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INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), |
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INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), |
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INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), |
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INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), |
|
INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), |
|
INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), |
|
INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), |
|
INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), |
|
INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), |
|
}; |
|
|
|
static struct intc_mask_reg mask_registers[] __initdata = { |
|
{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ |
|
{ 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, |
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0, ENABLED, ENABLED, ENABLED } }, |
|
{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ |
|
{ VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, |
|
{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ |
|
{ 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, |
|
{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ |
|
{ DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, |
|
{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ |
|
{ 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, |
|
{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ |
|
{ KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, |
|
{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ |
|
{ 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, |
|
{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ |
|
{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, |
|
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, |
|
{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ |
|
{ 0, ENABLED, ENABLED, ENABLED, |
|
0, 0, SCIFA_SCIFA2, SIU_SIUI } }, |
|
{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ |
|
{ 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, |
|
{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ |
|
{ 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, |
|
{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ |
|
{ 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, |
|
{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ |
|
{ 0,0,0,0,0,0,0,ATAPI_ATAPII } }, |
|
{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ |
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
|
}; |
|
|
|
static struct intc_prio_reg prio_registers[] __initdata = { |
|
{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, |
|
{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, |
|
{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, |
|
{ 0xa408000c, 0, 16, 4, /* IPRD */ { } }, |
|
{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, |
|
{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, |
|
{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, |
|
{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, |
|
{ 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, |
|
{ 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, |
|
{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, |
|
{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, |
|
{ 0xa4140010, 0, 32, 4, /* INTPRI00 */ |
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
|
}; |
|
|
|
static struct intc_sense_reg sense_registers[] __initdata = { |
|
{ 0xa414001c, 16, 2, /* ICR1 */ |
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
|
}; |
|
|
|
static struct intc_mask_reg ack_registers[] __initdata = { |
|
{ 0xa4140024, 0, 8, /* INTREQ00 */ |
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
|
}; |
|
|
|
static struct intc_desc intc_desc __initdata = { |
|
.name = "sh7723", |
|
.force_enable = ENABLED, |
|
.force_disable = DISABLED, |
|
.hw = INTC_HW_DESC(vectors, groups, mask_registers, |
|
prio_registers, sense_registers, ack_registers), |
|
}; |
|
|
|
void __init plat_irq_setup(void) |
|
{ |
|
register_intc_controller(&intc_desc); |
|
}
|
|
|