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265 lines
6.1 KiB
265 lines
6.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Performance events support for SH7750-style performance counters |
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* |
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* Copyright (C) 2009 Paul Mundt |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/perf_event.h> |
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#include <asm/processor.h> |
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#define PM_CR_BASE 0xff000084 /* 16-bit */ |
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#define PM_CTR_BASE 0xff100004 /* 32-bit */ |
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#define PMCR(n) (PM_CR_BASE + ((n) * 0x04)) |
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#define PMCTRH(n) (PM_CTR_BASE + 0x00 + ((n) * 0x08)) |
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#define PMCTRL(n) (PM_CTR_BASE + 0x04 + ((n) * 0x08)) |
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#define PMCR_PMM_MASK 0x0000003f |
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#define PMCR_CLKF 0x00000100 |
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#define PMCR_PMCLR 0x00002000 |
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#define PMCR_PMST 0x00004000 |
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#define PMCR_PMEN 0x00008000 |
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static struct sh_pmu sh7750_pmu; |
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/* |
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* There are a number of events supported by each counter (33 in total). |
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* Since we have 2 counters, each counter will take the event code as it |
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* corresponds to the PMCR PMM setting. Each counter can be configured |
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* independently. |
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* |
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* Event Code Description |
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* ---------- ----------- |
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* |
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* 0x01 Operand read access |
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* 0x02 Operand write access |
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* 0x03 UTLB miss |
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* 0x04 Operand cache read miss |
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* 0x05 Operand cache write miss |
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* 0x06 Instruction fetch (w/ cache) |
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* 0x07 Instruction TLB miss |
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* 0x08 Instruction cache miss |
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* 0x09 All operand accesses |
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* 0x0a All instruction accesses |
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* 0x0b OC RAM operand access |
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* 0x0d On-chip I/O space access |
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* 0x0e Operand access (r/w) |
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* 0x0f Operand cache miss (r/w) |
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* 0x10 Branch instruction |
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* 0x11 Branch taken |
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* 0x12 BSR/BSRF/JSR |
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* 0x13 Instruction execution |
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* 0x14 Instruction execution in parallel |
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* 0x15 FPU Instruction execution |
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* 0x16 Interrupt |
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* 0x17 NMI |
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* 0x18 trapa instruction execution |
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* 0x19 UBCA match |
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* 0x1a UBCB match |
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* 0x21 Instruction cache fill |
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* 0x22 Operand cache fill |
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* 0x23 Elapsed time |
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* 0x24 Pipeline freeze by I-cache miss |
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* 0x25 Pipeline freeze by D-cache miss |
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* 0x27 Pipeline freeze by branch instruction |
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* 0x28 Pipeline freeze by CPU register |
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* 0x29 Pipeline freeze by FPU |
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*/ |
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static const int sh7750_general_events[] = { |
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0023, |
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x000a, |
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0006, /* I-cache */ |
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[PERF_COUNT_HW_CACHE_MISSES] = 0x0008, /* I-cache */ |
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0010, |
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[PERF_COUNT_HW_BRANCH_MISSES] = -1, |
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[PERF_COUNT_HW_BUS_CYCLES] = -1, |
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}; |
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#define C(x) PERF_COUNT_HW_CACHE_##x |
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static const int sh7750_cache_events |
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[PERF_COUNT_HW_CACHE_MAX] |
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[PERF_COUNT_HW_CACHE_OP_MAX] |
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = |
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{ |
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[ C(L1D) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0x0001, |
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[ C(RESULT_MISS) ] = 0x0004, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = 0x0002, |
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[ C(RESULT_MISS) ] = 0x0005, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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}, |
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[ C(L1I) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0x0006, |
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[ C(RESULT_MISS) ] = 0x0008, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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}, |
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[ C(LL) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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}, |
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[ C(DTLB) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0x0003, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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}, |
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[ C(ITLB) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0x0007, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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}, |
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[ C(BPU) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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}, |
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[ C(NODE) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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}, |
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}; |
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static int sh7750_event_map(int event) |
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{ |
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return sh7750_general_events[event]; |
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} |
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static u64 sh7750_pmu_read(int idx) |
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{ |
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return (u64)((u64)(__raw_readl(PMCTRH(idx)) & 0xffff) << 32) | |
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__raw_readl(PMCTRL(idx)); |
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} |
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static void sh7750_pmu_disable(struct hw_perf_event *hwc, int idx) |
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{ |
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unsigned int tmp; |
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tmp = __raw_readw(PMCR(idx)); |
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tmp &= ~(PMCR_PMM_MASK | PMCR_PMEN); |
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__raw_writew(tmp, PMCR(idx)); |
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} |
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static void sh7750_pmu_enable(struct hw_perf_event *hwc, int idx) |
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{ |
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__raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx)); |
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__raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx)); |
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} |
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static void sh7750_pmu_disable_all(void) |
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{ |
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int i; |
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for (i = 0; i < sh7750_pmu.num_events; i++) |
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__raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i)); |
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} |
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static void sh7750_pmu_enable_all(void) |
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{ |
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int i; |
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for (i = 0; i < sh7750_pmu.num_events; i++) |
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__raw_writew(__raw_readw(PMCR(i)) | PMCR_PMEN, PMCR(i)); |
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} |
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static struct sh_pmu sh7750_pmu = { |
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.name = "sh7750", |
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.num_events = 2, |
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.event_map = sh7750_event_map, |
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.max_events = ARRAY_SIZE(sh7750_general_events), |
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.raw_event_mask = PMCR_PMM_MASK, |
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.cache_events = &sh7750_cache_events, |
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.read = sh7750_pmu_read, |
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.disable = sh7750_pmu_disable, |
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.enable = sh7750_pmu_enable, |
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.disable_all = sh7750_pmu_disable_all, |
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.enable_all = sh7750_pmu_enable_all, |
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}; |
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static int __init sh7750_pmu_init(void) |
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{ |
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/* |
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* Make sure this CPU actually has perf counters. |
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*/ |
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if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) { |
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pr_notice("HW perf events unsupported, software events only.\n"); |
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return -ENODEV; |
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} |
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return register_sh_pmu(&sh7750_pmu); |
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} |
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early_initcall(sh7750_pmu_init);
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