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509 lines
10 KiB
509 lines
10 KiB
/* SPDX-License-Identifier: GPL-2.0 |
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* |
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* arch/sh/kernel/cpu/sh3/entry.S |
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* |
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* Copyright (C) 1999, 2000, 2002 Niibe Yutaka |
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* Copyright (C) 2003 - 2012 Paul Mundt |
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*/ |
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#include <linux/sys.h> |
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#include <linux/errno.h> |
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#include <linux/linkage.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/thread_info.h> |
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#include <asm/unistd.h> |
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#include <cpu/mmu_context.h> |
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#include <asm/page.h> |
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#include <asm/cache.h> |
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! NOTE: |
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! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address |
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! to be jumped is too far, but it causes illegal slot exception. |
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/* |
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* entry.S contains the system-call and fault low-level handling routines. |
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* This also contains the timer-interrupt handler, as well as all interrupts |
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* and faults that can result in a task-switch. |
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* |
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* NOTE: This code handles signal-recognition, which happens every time |
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* after a timer-interrupt and after each system call. |
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* |
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* NOTE: This code uses a convention that instructions in the delay slot |
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* of a transfer-control instruction are indented by an extra space, thus: |
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* |
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* jmp @k0 ! control-transfer instruction |
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* ldc k1, ssr ! delay slot |
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* |
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* Stack layout in 'ret_from_syscall': |
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* ptrace needs to have all regs on the stack. |
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* if the order here is changed, it needs to be |
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* updated in ptrace.c and ptrace.h |
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* |
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* r0 |
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* ... |
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* r15 = stack pointer |
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* spc |
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* pr |
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* ssr |
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* gbr |
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* mach |
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* macl |
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* syscall # |
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* |
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*/ |
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/* Offsets to the stack */ |
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OFF_R0 = 0 /* Return value. New ABI also arg4 */ |
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OFF_R1 = 4 /* New ABI: arg5 */ |
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OFF_R2 = 8 /* New ABI: arg6 */ |
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OFF_R3 = 12 /* New ABI: syscall_nr */ |
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OFF_R4 = 16 /* New ABI: arg0 */ |
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OFF_R5 = 20 /* New ABI: arg1 */ |
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OFF_R6 = 24 /* New ABI: arg2 */ |
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OFF_R7 = 28 /* New ABI: arg3 */ |
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OFF_SP = (15*4) |
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OFF_PC = (16*4) |
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OFF_SR = (16*4+8) |
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OFF_TRA = (16*4+6*4) |
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#define k0 r0 |
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#define k1 r1 |
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#define k2 r2 |
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#define k3 r3 |
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#define k4 r4 |
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#define g_imask r6 /* r6_bank1 */ |
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#define k_g_imask r6_bank /* r6_bank1 */ |
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#define current r7 /* r7_bank1 */ |
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#include <asm/entry-macros.S> |
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/* |
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* Kernel mode register usage: |
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* k0 scratch |
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* k1 scratch |
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* k2 scratch (Exception code) |
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* k3 scratch (Return address) |
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* k4 scratch |
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* k5 reserved |
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* k6 Global Interrupt Mask (0--15 << 4) |
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* k7 CURRENT_THREAD_INFO (pointer to current thread info) |
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*/ |
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! |
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! TLB Miss / Initial Page write exception handling |
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! _and_ |
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! TLB hits, but the access violate the protection. |
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! It can be valid access, such as stack grow and/or C-O-W. |
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! |
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! |
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! Find the pmd/pte entry and loadtlb |
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! If it's not found, cause address error (SEGV) |
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! |
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! Although this could be written in assembly language (and it'd be faster), |
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! this first version depends *much* on C implementation. |
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! |
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#if defined(CONFIG_MMU) |
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.align 2 |
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ENTRY(tlb_miss_load) |
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bra call_handle_tlbmiss |
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mov #0, r5 |
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.align 2 |
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ENTRY(tlb_miss_store) |
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bra call_handle_tlbmiss |
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mov #FAULT_CODE_WRITE, r5 |
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.align 2 |
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ENTRY(initial_page_write) |
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bra call_handle_tlbmiss |
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mov #FAULT_CODE_INITIAL, r5 |
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.align 2 |
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ENTRY(tlb_protection_violation_load) |
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bra call_do_page_fault |
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mov #FAULT_CODE_PROT, r5 |
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.align 2 |
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ENTRY(tlb_protection_violation_store) |
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bra call_do_page_fault |
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mov #(FAULT_CODE_PROT | FAULT_CODE_WRITE), r5 |
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call_handle_tlbmiss: |
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mov.l 1f, r0 |
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mov r5, r8 |
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mov.l @r0, r6 |
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mov.l 2f, r0 |
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sts pr, r10 |
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jsr @r0 |
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mov r15, r4 |
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! |
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tst r0, r0 |
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bf/s 0f |
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lds r10, pr |
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rts |
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nop |
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0: |
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mov r8, r5 |
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call_do_page_fault: |
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mov.l 1f, r0 |
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mov.l @r0, r6 |
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mov.l 3f, r0 |
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mov.l 4f, r1 |
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mov r15, r4 |
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jmp @r0 |
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lds r1, pr |
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.align 2 |
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1: .long MMU_TEA |
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2: .long handle_tlbmiss |
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3: .long do_page_fault |
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4: .long ret_from_exception |
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.align 2 |
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ENTRY(address_error_load) |
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bra call_dae |
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mov #0,r5 ! writeaccess = 0 |
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.align 2 |
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ENTRY(address_error_store) |
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bra call_dae |
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mov #1,r5 ! writeaccess = 1 |
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.align 2 |
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call_dae: |
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mov.l 1f, r0 |
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mov.l @r0, r6 ! address |
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mov.l 2f, r0 |
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jmp @r0 |
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mov r15, r4 ! regs |
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.align 2 |
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1: .long MMU_TEA |
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2: .long do_address_error |
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#endif /* CONFIG_MMU */ |
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#if defined(CONFIG_SH_STANDARD_BIOS) |
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/* Unwind the stack and jmp to the debug entry */ |
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ENTRY(sh_bios_handler) |
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mov.l 1f, r8 |
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bsr restore_regs |
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nop |
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lds k2, pr ! restore pr |
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mov k4, r15 |
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! |
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mov.l 2f, k0 |
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mov.l @k0, k0 |
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jmp @k0 |
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ldc k3, ssr |
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.align 2 |
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1: .long 0x300000f0 |
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2: .long gdb_vbr_vector |
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#endif /* CONFIG_SH_STANDARD_BIOS */ |
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! restore_regs() |
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! - restore r0, r1, r2, r3, r4, r5, r6, r7 from the stack |
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! - switch bank |
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! - restore r8, r9, r10, r11, r12, r13, r14, r15 from the stack |
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! - restore spc, pr*, ssr, gbr, mach, macl, skip default tra |
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! k2 returns original pr |
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! k3 returns original sr |
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! k4 returns original stack pointer |
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! r8 passes SR bitmask, overwritten with restored data on return |
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! r9 trashed |
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! BL=0 on entry, on exit BL=1 (depending on r8). |
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ENTRY(restore_regs) |
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mov.l @r15+, r0 |
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mov.l @r15+, r1 |
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mov.l @r15+, r2 |
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mov.l @r15+, r3 |
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mov.l @r15+, r4 |
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mov.l @r15+, r5 |
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mov.l @r15+, r6 |
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mov.l @r15+, r7 |
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! |
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stc sr, r9 |
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or r8, r9 |
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ldc r9, sr |
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! |
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mov.l @r15+, r8 |
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mov.l @r15+, r9 |
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mov.l @r15+, r10 |
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mov.l @r15+, r11 |
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mov.l @r15+, r12 |
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mov.l @r15+, r13 |
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mov.l @r15+, r14 |
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mov.l @r15+, k4 ! original stack pointer |
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ldc.l @r15+, spc |
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mov.l @r15+, k2 ! original PR |
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mov.l @r15+, k3 ! original SR |
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ldc.l @r15+, gbr |
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lds.l @r15+, mach |
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lds.l @r15+, macl |
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rts |
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add #4, r15 ! Skip syscall number |
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restore_all: |
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mov.l 7f, r8 |
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bsr restore_regs |
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nop |
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lds k2, pr ! restore pr |
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! |
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! Calculate new SR value |
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mov k3, k2 ! original SR value |
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mov #0xfffffff0, k1 |
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extu.b k1, k1 |
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not k1, k1 |
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and k1, k2 ! Mask original SR value |
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! |
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mov k3, k0 ! Calculate IMASK-bits |
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shlr2 k0 |
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and #0x3c, k0 |
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cmp/eq #0x3c, k0 |
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bt/s 6f |
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shll2 k0 |
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mov g_imask, k0 |
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! |
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6: or k0, k2 ! Set the IMASK-bits |
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ldc k2, ssr |
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! |
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mov k4, r15 |
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rte |
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nop |
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.align 2 |
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5: .long 0x00001000 ! DSP |
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7: .long 0x30000000 |
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! common exception handler |
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#include "../../entry-common.S" |
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! Exception Vector Base |
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! |
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! Should be aligned page boundary. |
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! |
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.balign 4096,0,4096 |
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ENTRY(vbr_base) |
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.long 0 |
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! |
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! 0x100: General exception vector |
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! |
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.balign 256,0,256 |
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general_exception: |
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bra handle_exception |
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sts pr, k3 ! save original pr value in k3 |
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! prepare_stack() |
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! - roll back gRB |
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! - switch to kernel stack |
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! k0 returns original sp (after roll back) |
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! k1 trashed |
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! k2 trashed |
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prepare_stack: |
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#ifdef CONFIG_GUSA |
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! Check for roll back gRB (User and Kernel) |
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mov r15, k0 |
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shll k0 |
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bf/s 1f |
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shll k0 |
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bf/s 1f |
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stc spc, k1 |
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stc r0_bank, k0 |
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cmp/hs k0, k1 ! test k1 (saved PC) >= k0 (saved r0) |
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bt/s 2f |
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stc r1_bank, k1 |
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add #-2, k0 |
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add r15, k0 |
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ldc k0, spc ! PC = saved r0 + r15 - 2 |
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2: mov k1, r15 ! SP = r1 |
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1: |
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#endif |
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! Switch to kernel stack if needed |
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stc ssr, k0 ! Is it from kernel space? |
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shll k0 ! Check MD bit (bit30) by shifting it into... |
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shll k0 ! ...the T bit |
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bt/s 1f ! It's a kernel to kernel transition. |
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mov r15, k0 ! save original stack to k0 |
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/* User space to kernel */ |
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mov #(THREAD_SIZE >> 10), k1 |
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shll8 k1 ! k1 := THREAD_SIZE |
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shll2 k1 |
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add current, k1 |
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mov k1, r15 ! change to kernel stack |
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! |
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1: |
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rts |
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nop |
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! |
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! 0x400: Instruction and Data TLB miss exception vector |
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! |
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.balign 1024,0,1024 |
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tlb_miss: |
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sts pr, k3 ! save original pr value in k3 |
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handle_exception: |
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mova exception_data, k0 |
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! Setup stack and save DSP context (k0 contains original r15 on return) |
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bsr prepare_stack |
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PREF(k0) |
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! Save registers / Switch to bank 0 |
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mov.l 5f, k2 ! vector register address |
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mov.l 1f, k4 ! SR bits to clear in k4 |
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bsr save_regs ! needs original pr value in k3 |
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mov.l @k2, k2 ! read out vector and keep in k2 |
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handle_exception_special: |
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setup_frame_reg |
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! Setup return address and jump to exception handler |
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mov.l 7f, r9 ! fetch return address |
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stc r2_bank, r0 ! k2 (vector) |
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mov.l 6f, r10 |
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shlr2 r0 |
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shlr r0 |
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mov.l @(r0, r10), r10 |
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jmp @r10 |
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lds r9, pr ! put return address in pr |
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.align L1_CACHE_SHIFT |
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! save_regs() |
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! - save default tra, macl, mach, gbr, ssr, pr* and spc on the stack |
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! - save r15*, r14, r13, r12, r11, r10, r9, r8 on the stack |
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! - switch bank |
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! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack |
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! k0 contains original stack pointer* |
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! k1 trashed |
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! k3 passes original pr* |
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! k4 passes SR bitmask |
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! BL=1 on entry, on exit BL=0. |
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ENTRY(save_regs) |
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mov #-1, r1 |
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mov.l k1, @-r15 ! set TRA (default: -1) |
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sts.l macl, @-r15 |
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sts.l mach, @-r15 |
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stc.l gbr, @-r15 |
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stc.l ssr, @-r15 |
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mov.l k3, @-r15 ! original pr in k3 |
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stc.l spc, @-r15 |
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mov.l k0, @-r15 ! original stack pointer in k0 |
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mov.l r14, @-r15 |
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mov.l r13, @-r15 |
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mov.l r12, @-r15 |
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mov.l r11, @-r15 |
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mov.l r10, @-r15 |
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mov.l r9, @-r15 |
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mov.l r8, @-r15 |
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mov.l 0f, k3 ! SR bits to set in k3 |
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! fall-through |
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! save_low_regs() |
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! - modify SR for bank switch |
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! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack |
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! k3 passes bits to set in SR |
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! k4 passes bits to clear in SR |
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ENTRY(save_low_regs) |
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stc sr, r8 |
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or k3, r8 |
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and k4, r8 |
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ldc r8, sr |
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mov.l r7, @-r15 |
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mov.l r6, @-r15 |
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mov.l r5, @-r15 |
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mov.l r4, @-r15 |
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mov.l r3, @-r15 |
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mov.l r2, @-r15 |
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mov.l r1, @-r15 |
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rts |
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mov.l r0, @-r15 |
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! |
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! 0x600: Interrupt / NMI vector |
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! |
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.balign 512,0,512 |
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ENTRY(handle_interrupt) |
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sts pr, k3 ! save original pr value in k3 |
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mova exception_data, k0 |
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! Setup stack and save DSP context (k0 contains original r15 on return) |
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bsr prepare_stack |
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PREF(k0) |
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! Save registers / Switch to bank 0 |
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mov.l 1f, k4 ! SR bits to clear in k4 |
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bsr save_regs ! needs original pr value in k3 |
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mov #-1, k2 ! default vector kept in k2 |
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setup_frame_reg |
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stc sr, r0 ! get status register |
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shlr2 r0 |
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and #0x3c, r0 |
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cmp/eq #0x3c, r0 |
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bf 9f |
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TRACE_IRQS_OFF |
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9: |
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! Setup return address and jump to do_IRQ |
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mov.l 4f, r9 ! fetch return address |
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lds r9, pr ! put return address in pr |
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mov.l 2f, r4 |
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mov.l 3f, r9 |
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mov.l @r4, r4 ! pass INTEVT vector as arg0 |
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shlr2 r4 |
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shlr r4 |
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mov r4, r0 ! save vector->jmp table offset for later |
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shlr2 r4 ! vector to IRQ# conversion |
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add #-0x10, r4 |
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cmp/pz r4 ! is it a valid IRQ? |
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bt 10f |
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/* |
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* We got here as a result of taking the INTEVT path for something |
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* that isn't a valid hard IRQ, therefore we bypass the do_IRQ() |
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* path and special case the event dispatch instead. This is the |
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* expected path for the NMI (and any other brilliantly implemented |
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* exception), which effectively wants regular exception dispatch |
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* but is unfortunately reported through INTEVT rather than |
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* EXPEVT. Grr. |
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*/ |
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mov.l 6f, r9 |
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mov.l @(r0, r9), r9 |
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jmp @r9 |
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mov r15, r8 ! trap handlers take saved regs in r8 |
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10: |
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jmp @r9 ! Off to do_IRQ() we go. |
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mov r15, r5 ! pass saved registers as arg1 |
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ENTRY(exception_none) |
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rts |
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nop |
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.align L1_CACHE_SHIFT |
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exception_data: |
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0: .long 0x000080f0 ! FD=1, IMASK=15 |
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1: .long 0xcfffffff ! RB=0, BL=0 |
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2: .long INTEVT |
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3: .long do_IRQ |
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4: .long ret_from_irq |
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5: .long EXPEVT |
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6: .long exception_handling_table |
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7: .long ret_from_exception
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