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181 lines
4.7 KiB
181 lines
4.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* arch/sh/kernel/cpu/sh2a/clock-sh7269.c |
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* |
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* SH7269 clock framework support |
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* |
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* Copyright (C) 2012 Phil Edworthy |
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*/ |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/io.h> |
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#include <linux/clkdev.h> |
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#include <asm/clock.h> |
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/* SH7269 registers */ |
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#define FRQCR 0xfffe0010 |
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#define STBCR3 0xfffe0408 |
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#define STBCR4 0xfffe040c |
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#define STBCR5 0xfffe0410 |
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#define STBCR6 0xfffe0414 |
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#define STBCR7 0xfffe0418 |
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#define PLL_RATE 20 |
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/* Fixed 32 KHz root clock for RTC */ |
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static struct clk r_clk = { |
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.rate = 32768, |
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}; |
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/* |
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* Default rate for the root input clock, reset this with clk_set_rate() |
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* from the platform code. |
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*/ |
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static struct clk extal_clk = { |
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.rate = 13340000, |
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}; |
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static unsigned long pll_recalc(struct clk *clk) |
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{ |
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return clk->parent->rate * PLL_RATE; |
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} |
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static struct sh_clk_ops pll_clk_ops = { |
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.recalc = pll_recalc, |
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}; |
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static struct clk pll_clk = { |
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.ops = &pll_clk_ops, |
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.parent = &extal_clk, |
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.flags = CLK_ENABLE_ON_INIT, |
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}; |
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static unsigned long peripheral0_recalc(struct clk *clk) |
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{ |
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return clk->parent->rate / 8; |
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} |
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static struct sh_clk_ops peripheral0_clk_ops = { |
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.recalc = peripheral0_recalc, |
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}; |
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static struct clk peripheral0_clk = { |
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.ops = &peripheral0_clk_ops, |
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.parent = &pll_clk, |
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.flags = CLK_ENABLE_ON_INIT, |
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}; |
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static unsigned long peripheral1_recalc(struct clk *clk) |
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{ |
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return clk->parent->rate / 4; |
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} |
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static struct sh_clk_ops peripheral1_clk_ops = { |
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.recalc = peripheral1_recalc, |
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}; |
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static struct clk peripheral1_clk = { |
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.ops = &peripheral1_clk_ops, |
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.parent = &pll_clk, |
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.flags = CLK_ENABLE_ON_INIT, |
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}; |
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struct clk *main_clks[] = { |
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&r_clk, |
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&extal_clk, |
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&pll_clk, |
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&peripheral0_clk, |
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&peripheral1_clk, |
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}; |
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static int div2[] = { 1, 2, 0, 4 }; |
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static struct clk_div_mult_table div4_div_mult_table = { |
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.divisors = div2, |
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.nr_divisors = ARRAY_SIZE(div2), |
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}; |
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static struct clk_div4_table div4_table = { |
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.div_mult_table = &div4_div_mult_table, |
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}; |
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enum { DIV4_I, DIV4_B, |
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DIV4_NR }; |
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#define DIV4(_reg, _bit, _mask, _flags) \ |
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) |
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/* The mask field specifies the div2 entries that are valid */ |
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struct clk div4_clks[DIV4_NR] = { |
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[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT |
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| CLK_ENABLE_ON_INIT), |
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[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT |
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| CLK_ENABLE_ON_INIT), |
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}; |
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enum { MSTP72, |
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MSTP60, |
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MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, |
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MSTP35, MSTP32, MSTP30, |
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MSTP_NR }; |
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static struct clk mstp_clks[MSTP_NR] = { |
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[MSTP72] = SH_CLK_MSTP8(&peripheral0_clk, STBCR7, 2, 0), /* CMT */ |
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[MSTP60] = SH_CLK_MSTP8(&peripheral1_clk, STBCR6, 0, 0), /* USB */ |
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[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ |
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[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ |
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[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ |
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[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */ |
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[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */ |
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[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */ |
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[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */ |
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[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */ |
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[MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */ |
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[MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */ |
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[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */ |
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}; |
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static struct clk_lookup lookups[] = { |
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/* main clocks */ |
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CLKDEV_CON_ID("rclk", &r_clk), |
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CLKDEV_CON_ID("extal", &extal_clk), |
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CLKDEV_CON_ID("pll_clk", &pll_clk), |
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CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk), |
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/* DIV4 clocks */ |
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), |
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CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), |
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/* MSTP clocks */ |
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CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP47]), |
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CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP46]), |
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CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP45]), |
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CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP44]), |
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CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP43]), |
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CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP42]), |
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CLKDEV_ICK_ID("fck", "sh-sci.6", &mstp_clks[MSTP41]), |
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CLKDEV_ICK_ID("fck", "sh-sci.7", &mstp_clks[MSTP40]), |
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CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]), |
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CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]), |
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CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]), |
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CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]), |
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CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]), |
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}; |
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int __init arch_clk_init(void) |
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{ |
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int k, ret = 0; |
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) |
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ret = clk_register(main_clks[k]); |
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clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
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if (!ret) |
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); |
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if (!ret) |
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); |
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return ret; |
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}
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