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366 lines
8.3 KiB
366 lines
8.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* arch/sh/kernel/cpu/init.c |
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* |
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* CPU init code |
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* |
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* Copyright (C) 2002 - 2009 Paul Mundt |
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* Copyright (C) 2003 Richard Curnow |
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*/ |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/mm.h> |
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#include <linux/log2.h> |
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#include <asm/mmu_context.h> |
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#include <asm/processor.h> |
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#include <linux/uaccess.h> |
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#include <asm/page.h> |
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#include <asm/cacheflush.h> |
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#include <asm/cache.h> |
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#include <asm/elf.h> |
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#include <asm/io.h> |
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#include <asm/smp.h> |
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#include <asm/sh_bios.h> |
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#include <asm/setup.h> |
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#ifdef CONFIG_SH_FPU |
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#define cpu_has_fpu 1 |
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#else |
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#define cpu_has_fpu 0 |
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#endif |
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#ifdef CONFIG_SH_DSP |
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#define cpu_has_dsp 1 |
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#else |
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#define cpu_has_dsp 0 |
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#endif |
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/* |
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* Generic wrapper for command line arguments to disable on-chip |
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* peripherals (nofpu, nodsp, and so forth). |
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*/ |
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#define onchip_setup(x) \ |
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static int x##_disabled = !cpu_has_##x; \ |
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\ |
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static int x##_setup(char *opts) \ |
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{ \ |
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x##_disabled = 1; \ |
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return 1; \ |
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} \ |
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__setup("no" __stringify(x), x##_setup); |
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onchip_setup(fpu); |
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onchip_setup(dsp); |
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#ifdef CONFIG_SPECULATIVE_EXECUTION |
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#define CPUOPM 0xff2f0000 |
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#define CPUOPM_RABD (1 << 5) |
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static void speculative_execution_init(void) |
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{ |
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/* Clear RABD */ |
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__raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); |
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/* Flush the update */ |
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(void)__raw_readl(CPUOPM); |
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ctrl_barrier(); |
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} |
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#else |
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#define speculative_execution_init() do { } while (0) |
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#endif |
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#ifdef CONFIG_CPU_SH4A |
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#define EXPMASK 0xff2f0004 |
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#define EXPMASK_RTEDS (1 << 0) |
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#define EXPMASK_BRDSSLP (1 << 1) |
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#define EXPMASK_MMCAW (1 << 4) |
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static void expmask_init(void) |
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{ |
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unsigned long expmask = __raw_readl(EXPMASK); |
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/* |
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* Future proofing. |
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* |
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* Disable support for slottable sleep instruction, non-nop |
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* instructions in the rte delay slot, and associative writes to |
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* the memory-mapped cache array. |
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*/ |
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expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP | EXPMASK_MMCAW); |
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__raw_writel(expmask, EXPMASK); |
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ctrl_barrier(); |
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} |
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#else |
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#define expmask_init() do { } while (0) |
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#endif |
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/* 2nd-level cache init */ |
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void __attribute__ ((weak)) l2_cache_init(void) |
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{ |
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} |
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/* |
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* Generic first-level cache init |
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*/ |
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#if !defined(CONFIG_CPU_J2) |
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static void cache_init(void) |
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{ |
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unsigned long ccr, flags; |
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jump_to_uncached(); |
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ccr = __raw_readl(SH_CCR); |
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/* |
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* At this point we don't know whether the cache is enabled or not - a |
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* bootloader may have enabled it. There are at least 2 things that |
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* could be dirty in the cache at this point: |
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* 1. kernel command line set up by boot loader |
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* 2. spilled registers from the prolog of this function |
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* => before re-initialising the cache, we must do a purge of the whole |
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* cache out to memory for safety. As long as nothing is spilled |
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* during the loop to lines that have already been done, this is safe. |
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* - RPC |
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*/ |
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if (ccr & CCR_CACHE_ENABLE) { |
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unsigned long ways, waysize, addrstart; |
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waysize = current_cpu_data.dcache.sets; |
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#ifdef CCR_CACHE_ORA |
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/* |
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* If the OC is already in RAM mode, we only have |
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* half of the entries to flush.. |
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*/ |
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if (ccr & CCR_CACHE_ORA) |
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waysize >>= 1; |
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#endif |
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waysize <<= current_cpu_data.dcache.entry_shift; |
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#ifdef CCR_CACHE_EMODE |
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/* If EMODE is not set, we only have 1 way to flush. */ |
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if (!(ccr & CCR_CACHE_EMODE)) |
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ways = 1; |
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else |
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#endif |
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ways = current_cpu_data.dcache.ways; |
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addrstart = CACHE_OC_ADDRESS_ARRAY; |
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do { |
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unsigned long addr; |
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for (addr = addrstart; |
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addr < addrstart + waysize; |
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addr += current_cpu_data.dcache.linesz) |
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__raw_writel(0, addr); |
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addrstart += current_cpu_data.dcache.way_incr; |
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} while (--ways); |
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} |
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/* |
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* Default CCR values .. enable the caches |
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* and invalidate them immediately.. |
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*/ |
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flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; |
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#ifdef CCR_CACHE_EMODE |
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/* Force EMODE if possible */ |
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if (current_cpu_data.dcache.ways > 1) |
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flags |= CCR_CACHE_EMODE; |
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else |
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flags &= ~CCR_CACHE_EMODE; |
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#endif |
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#if defined(CONFIG_CACHE_WRITETHROUGH) |
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/* Write-through */ |
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flags |= CCR_CACHE_WT; |
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#elif defined(CONFIG_CACHE_WRITEBACK) |
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/* Write-back */ |
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flags |= CCR_CACHE_CB; |
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#else |
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/* Off */ |
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flags &= ~CCR_CACHE_ENABLE; |
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#endif |
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l2_cache_init(); |
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__raw_writel(flags, SH_CCR); |
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back_to_cached(); |
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} |
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#else |
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#define cache_init() do { } while (0) |
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#endif |
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#define CSHAPE(totalsize, linesize, assoc) \ |
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((totalsize & ~0xff) | (linesize << 4) | assoc) |
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#define CACHE_DESC_SHAPE(desc) \ |
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CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways) |
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static void detect_cache_shape(void) |
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{ |
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l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); |
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if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) |
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l1i_cache_shape = l1d_cache_shape; |
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else |
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l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); |
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if (current_cpu_data.flags & CPU_HAS_L2_CACHE) |
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l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache); |
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else |
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l2_cache_shape = -1; /* No S-cache */ |
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} |
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static void fpu_init(void) |
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{ |
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/* Disable the FPU */ |
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if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) { |
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printk("FPU Disabled\n"); |
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current_cpu_data.flags &= ~CPU_HAS_FPU; |
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} |
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disable_fpu(); |
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clear_used_math(); |
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} |
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#ifdef CONFIG_SH_DSP |
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static void release_dsp(void) |
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{ |
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unsigned long sr; |
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/* Clear SR.DSP bit */ |
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__asm__ __volatile__ ( |
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"stc\tsr, %0\n\t" |
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"and\t%1, %0\n\t" |
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"ldc\t%0, sr\n\t" |
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: "=&r" (sr) |
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: "r" (~SR_DSP) |
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); |
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} |
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static void dsp_init(void) |
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{ |
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unsigned long sr; |
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/* |
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* Set the SR.DSP bit, wait for one instruction, and then read |
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* back the SR value. |
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*/ |
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__asm__ __volatile__ ( |
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"stc\tsr, %0\n\t" |
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"or\t%1, %0\n\t" |
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"ldc\t%0, sr\n\t" |
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"nop\n\t" |
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"stc\tsr, %0\n\t" |
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: "=&r" (sr) |
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: "r" (SR_DSP) |
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); |
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/* If the DSP bit is still set, this CPU has a DSP */ |
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if (sr & SR_DSP) |
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current_cpu_data.flags |= CPU_HAS_DSP; |
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/* Disable the DSP */ |
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if (dsp_disabled && (current_cpu_data.flags & CPU_HAS_DSP)) { |
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printk("DSP Disabled\n"); |
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current_cpu_data.flags &= ~CPU_HAS_DSP; |
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} |
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/* Now that we've determined the DSP status, clear the DSP bit. */ |
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release_dsp(); |
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} |
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#else |
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static inline void dsp_init(void) { } |
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#endif /* CONFIG_SH_DSP */ |
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/** |
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* cpu_init |
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* |
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* This is our initial entry point for each CPU, and is invoked on the |
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* boot CPU prior to calling start_kernel(). For SMP, a combination of |
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* this and start_secondary() will bring up each processor to a ready |
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* state prior to hand forking the idle loop. |
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* |
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* We do all of the basic processor init here, including setting up |
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* the caches, FPU, DSP, etc. By the time start_kernel() is hit (and |
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* subsequently platform_setup()) things like determining the CPU |
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* subtype and initial configuration will all be done. |
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* |
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* Each processor family is still responsible for doing its own probing |
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* and cache configuration in cpu_probe(). |
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*/ |
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asmlinkage void cpu_init(void) |
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{ |
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current_thread_info()->cpu = hard_smp_processor_id(); |
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/* First, probe the CPU */ |
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cpu_probe(); |
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if (current_cpu_data.type == CPU_SH_NONE) |
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panic("Unknown CPU"); |
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/* First setup the rest of the I-cache info */ |
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current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - |
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current_cpu_data.icache.linesz; |
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current_cpu_data.icache.way_size = current_cpu_data.icache.sets * |
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current_cpu_data.icache.linesz; |
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/* And the D-cache too */ |
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current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - |
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current_cpu_data.dcache.linesz; |
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current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * |
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current_cpu_data.dcache.linesz; |
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/* Init the cache */ |
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cache_init(); |
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if (raw_smp_processor_id() == 0) { |
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#ifdef CONFIG_MMU |
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shm_align_mask = max_t(unsigned long, |
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current_cpu_data.dcache.way_size - 1, |
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PAGE_SIZE - 1); |
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#else |
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shm_align_mask = PAGE_SIZE - 1; |
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#endif |
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/* Boot CPU sets the cache shape */ |
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detect_cache_shape(); |
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} |
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fpu_init(); |
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dsp_init(); |
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/* |
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* Initialize the per-CPU ASID cache very early, since the |
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* TLB flushing routines depend on this being setup. |
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*/ |
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current_cpu_data.asid_cache = NO_CONTEXT; |
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current_cpu_data.phys_bits = __in_29bit_mode() ? 29 : 32; |
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speculative_execution_init(); |
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expmask_init(); |
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/* Do the rest of the boot processor setup */ |
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if (raw_smp_processor_id() == 0) { |
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/* Save off the BIOS VBR, if there is one */ |
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sh_bios_vbr_init(); |
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/* |
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* Setup VBR for boot CPU. Secondary CPUs do this through |
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* start_secondary(). |
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*/ |
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per_cpu_trap_init(); |
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/* |
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* Boot processor to setup the FP and extended state |
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* context info. |
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*/ |
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init_thread_xstate(); |
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} |
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}
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