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418 lines
11 KiB
418 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright IBM Corp. 1999, 2010 |
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* |
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* Author(s): Hartmut Penner <hp@de.ibm.com> |
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* Martin Schwidefsky <schwidefsky@de.ibm.com> |
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* Rob van der Heij <rvdhei@iae.nl> |
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* Heiko Carstens <heiko.carstens@de.ibm.com> |
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* |
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* There are 5 different IPL methods |
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* 1) load the image directly into ram at address 0 and do an PSW restart |
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* 2) linload will load the image from address 0x10000 to memory 0x10000 |
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* and start the code thru LPSW 0x0008000080010000 (VM only, deprecated) |
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* 3) generate the tape ipl header, store the generated image on a tape |
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* and ipl from it |
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* In case of SL tape you need to IPL 5 times to get past VOL1 etc |
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* 4) generate the vm reader ipl header, move the generated image to the |
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* VM reader (use option NOH!) and do a ipl from reader (VM only) |
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* 5) direct call of start by the SALIPL loader |
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* We use the cpuid to distinguish between VM and native ipl |
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* params for kernel are pushed to 0x10400 (see setup.h) |
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* |
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*/ |
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#include <linux/init.h> |
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#include <linux/linkage.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/thread_info.h> |
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#include <asm/page.h> |
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#include <asm/ptrace.h> |
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#include "boot.h" |
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#define ARCH_OFFSET 4 |
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__HEAD |
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#define IPL_BS 0x730 |
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.org 0 |
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.long 0x00080000,0x80000000+iplstart # The first 24 bytes are loaded |
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.long 0x02000018,0x60000050 # by ipl to addresses 0-23. |
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.long 0x02000068,0x60000050 # (a PSW and two CCWs). |
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.fill 80-24,1,0x40 # bytes 24-79 are discarded !! |
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.long 0x020000f0,0x60000050 # The next 160 byte are loaded |
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.long 0x02000140,0x60000050 # to addresses 0x18-0xb7 |
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.long 0x02000190,0x60000050 # They form the continuation |
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.long 0x020001e0,0x60000050 # of the CCW program started |
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.long 0x02000230,0x60000050 # by ipl and load the range |
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.long 0x02000280,0x60000050 # 0x0f0-0x730 from the image |
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.long 0x020002d0,0x60000050 # to the range 0x0f0-0x730 |
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.long 0x02000320,0x60000050 # in memory. At the end of |
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.long 0x02000370,0x60000050 # the channel program the PSW |
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.long 0x020003c0,0x60000050 # at location 0 is loaded. |
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.long 0x02000410,0x60000050 # Initial processing starts |
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.long 0x02000460,0x60000050 # at 0x200 = iplstart. |
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.long 0x020004b0,0x60000050 |
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.long 0x02000500,0x60000050 |
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.long 0x02000550,0x60000050 |
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.long 0x020005a0,0x60000050 |
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.long 0x020005f0,0x60000050 |
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.long 0x02000640,0x60000050 |
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.long 0x02000690,0x60000050 |
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.long 0x020006e0,0x20000050 |
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.org __LC_RST_NEW_PSW # 0x1a0 |
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.quad 0,iplstart |
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.org __LC_EXT_NEW_PSW # 0x1b0 |
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.quad 0x0002000180000000,0x1b0 # disabled wait |
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.org __LC_PGM_NEW_PSW # 0x1d0 |
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.quad 0x0000000180000000,startup_pgm_check_handler |
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.org __LC_IO_NEW_PSW # 0x1f0 |
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.quad 0x0002000180000000,0x1f0 # disabled wait |
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.org 0x200 |
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# |
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# subroutine to wait for end I/O |
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# |
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.Lirqwait: |
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mvc __LC_IO_NEW_PSW(16),.Lnewpsw # set up IO interrupt psw |
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lpsw .Lwaitpsw |
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.Lioint: |
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br %r14 |
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.align 8 |
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.Lnewpsw: |
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.quad 0x0000000080000000,.Lioint |
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.Lwaitpsw: |
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.long 0x020a0000,0x80000000+.Lioint |
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# |
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# subroutine for loading cards from the reader |
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# |
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.Lloader: |
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la %r4,0(%r14) |
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la %r3,.Lorb # r2 = address of orb into r2 |
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la %r5,.Lirb # r4 = address of irb |
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la %r6,.Lccws |
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la %r7,20 |
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.Linit: |
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st %r2,4(%r6) # initialize CCW data addresses |
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la %r2,0x50(%r2) |
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la %r6,8(%r6) |
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bct 7,.Linit |
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lctl %c6,%c6,.Lcr6 # set IO subclass mask |
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slr %r2,%r2 |
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.Lldlp: |
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ssch 0(%r3) # load chunk of 1600 bytes |
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bnz .Llderr |
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.Lwait4irq: |
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bas %r14,.Lirqwait |
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c %r1,__LC_SUBCHANNEL_ID # compare subchannel number |
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bne .Lwait4irq |
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tsch 0(%r5) |
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slr %r0,%r0 |
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ic %r0,8(%r5) # get device status |
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chi %r0,8 # channel end ? |
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be .Lcont |
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chi %r0,12 # channel end + device end ? |
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be .Lcont |
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l %r0,4(%r5) |
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s %r0,8(%r3) # r0/8 = number of ccws executed |
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mhi %r0,10 # *10 = number of bytes in ccws |
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lh %r3,10(%r5) # get residual count |
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sr %r0,%r3 # #ccws*80-residual=#bytes read |
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ar %r2,%r0 |
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br %r4 # r2 contains the total size |
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.Lcont: |
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ahi %r2,0x640 # add 0x640 to total size |
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la %r6,.Lccws |
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la %r7,20 |
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.Lincr: |
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l %r0,4(%r6) # update CCW data addresses |
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ahi %r0,0x640 |
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st %r0,4(%r6) |
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ahi %r6,8 |
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bct 7,.Lincr |
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b .Lldlp |
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.Llderr: |
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lpsw .Lcrash |
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.align 8 |
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.Lorb: .long 0x00000000,0x0080ff00,.Lccws |
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.Lirb: .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 |
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.Lcr6: .long 0xff000000 |
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.Lloadp:.long 0,0 |
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.align 8 |
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.Lcrash:.long 0x000a0000,0x00000000 |
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.align 8 |
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.Lccws: .rept 19 |
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.long 0x02600050,0x00000000 |
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.endr |
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.long 0x02200050,0x00000000 |
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iplstart: |
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mvi __LC_AR_MODE_ID,1 # set esame flag |
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slr %r0,%r0 # set cpuid to zero |
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lhi %r1,2 # mode 2 = esame (dump) |
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sigp %r1,%r0,0x12 # switch to esame mode |
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bras %r13,0f |
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.fill 16,4,0x0 |
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0: lmh %r0,%r15,0(%r13) # clear high-order half of gprs |
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sam31 # switch to 31 bit addressing mode |
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lh %r1,__LC_SUBCHANNEL_ID # test if subchannel number |
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bct %r1,.Lnoload # is valid |
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l %r1,__LC_SUBCHANNEL_ID # load ipl subchannel number |
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la %r2,IPL_BS # load start address |
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bas %r14,.Lloader # load rest of ipl image |
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l %r12,.Lparm # pointer to parameter area |
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st %r1,IPL_DEVICE+ARCH_OFFSET-PARMAREA(%r12) # save ipl device number |
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# |
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# load parameter file from ipl device |
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# |
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.Lagain1: |
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l %r2,.Linitrd # ramdisk loc. is temp |
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bas %r14,.Lloader # load parameter file |
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ltr %r2,%r2 # got anything ? |
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bz .Lnopf |
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chi %r2,895 |
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bnh .Lnotrunc |
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la %r2,895 |
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.Lnotrunc: |
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l %r4,.Linitrd |
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clc 0(3,%r4),.L_hdr # if it is HDRx |
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bz .Lagain1 # skip dataset header |
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clc 0(3,%r4),.L_eof # if it is EOFx |
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bz .Lagain1 # skip dateset trailer |
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la %r5,0(%r4,%r2) |
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lr %r3,%r2 |
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la %r3,COMMAND_LINE-PARMAREA(%r12) # load adr. of command line |
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mvc 0(256,%r3),0(%r4) |
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mvc 256(256,%r3),256(%r4) |
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mvc 512(256,%r3),512(%r4) |
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mvc 768(122,%r3),768(%r4) |
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slr %r0,%r0 |
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b .Lcntlp |
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.Ldelspc: |
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ic %r0,0(%r2,%r3) |
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chi %r0,0x20 # is it a space ? |
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be .Lcntlp |
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ahi %r2,1 |
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b .Leolp |
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.Lcntlp: |
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brct %r2,.Ldelspc |
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.Leolp: |
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slr %r0,%r0 |
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stc %r0,0(%r2,%r3) # terminate buffer |
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.Lnopf: |
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# |
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# load ramdisk from ipl device |
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# |
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.Lagain2: |
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l %r2,.Linitrd # addr of ramdisk |
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st %r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) |
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bas %r14,.Lloader # load ramdisk |
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st %r2,INITRD_SIZE+ARCH_OFFSET-PARMAREA(%r12) # store size of rd |
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ltr %r2,%r2 |
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bnz .Lrdcont |
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st %r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) # no ramdisk found |
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.Lrdcont: |
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l %r2,.Linitrd |
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clc 0(3,%r2),.L_hdr # skip HDRx and EOFx |
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bz .Lagain2 |
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clc 0(3,%r2),.L_eof |
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bz .Lagain2 |
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# |
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# reset files in VM reader |
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# |
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stidp .Lcpuid # store cpuid |
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tm .Lcpuid,0xff # running VM ? |
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bno .Lnoreset |
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la %r2,.Lreset |
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lhi %r3,26 |
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diag %r2,%r3,8 |
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la %r5,.Lirb |
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stsch 0(%r5) # check if irq is pending |
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tm 30(%r5),0x0f # by verifying if any of the |
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bnz .Lwaitforirq # activity or status control |
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tm 31(%r5),0xff # bits is set in the schib |
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bz .Lnoreset |
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.Lwaitforirq: |
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bas %r14,.Lirqwait # wait for IO interrupt |
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c %r1,__LC_SUBCHANNEL_ID # compare subchannel number |
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bne .Lwaitforirq |
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la %r5,.Lirb |
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tsch 0(%r5) |
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.Lnoreset: |
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b .Lnoload |
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# |
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# everything loaded, go for it |
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# |
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.Lnoload: |
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l %r1,.Lstartup |
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br %r1 |
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.Linitrd:.long _end # default address of initrd |
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.Lparm: .long PARMAREA |
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.Lstartup: .long startup |
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.Lreset:.byte 0xc3,0xc8,0xc1,0xd5,0xc7,0xc5,0x40,0xd9,0xc4,0xd9,0x40 |
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.byte 0xc1,0xd3,0xd3,0x40,0xd2,0xc5,0xc5,0xd7,0x40,0xd5,0xd6 |
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.byte 0xc8,0xd6,0xd3,0xc4 # "change rdr all keep nohold" |
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.L_eof: .long 0xc5d6c600 /* C'EOF' */ |
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.L_hdr: .long 0xc8c4d900 /* C'HDR' */ |
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.align 8 |
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.Lcpuid:.fill 8,1,0 |
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# |
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# startup-code at 0x10000, running in absolute addressing mode |
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# this is called either by the ipl loader or directly by PSW restart |
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# or linload or SALIPL |
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# |
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.org 0x10000 |
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SYM_CODE_START(startup) |
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j startup_normal |
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.org EP_OFFSET |
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# |
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# This is a list of s390 kernel entry points. At address 0x1000f the number of |
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# valid entry points is stored. |
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# |
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# IMPORTANT: Do not change this table, it is s390 kernel ABI! |
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# |
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.ascii EP_STRING |
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.byte 0x00,0x01 |
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# |
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# kdump startup-code at 0x10010, running in 64 bit absolute addressing mode |
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# |
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.org 0x10010 |
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j startup_kdump |
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SYM_CODE_END(startup) |
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SYM_CODE_START_LOCAL(startup_normal) |
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mvi __LC_AR_MODE_ID,1 # set esame flag |
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slr %r0,%r0 # set cpuid to zero |
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lhi %r1,2 # mode 2 = esame (dump) |
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sigp %r1,%r0,0x12 # switch to esame mode |
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bras %r13,0f |
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.fill 16,4,0x0 |
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0: lmh %r0,%r15,0(%r13) # clear high-order half of gprs |
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sam64 # switch to 64 bit addressing mode |
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basr %r13,0 # get base |
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.LPG0: |
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mvc __LC_EXT_NEW_PSW(16),.Lext_new_psw-.LPG0(%r13) |
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mvc __LC_PGM_NEW_PSW(16),.Lpgm_new_psw-.LPG0(%r13) |
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mvc __LC_IO_NEW_PSW(16),.Lio_new_psw-.LPG0(%r13) |
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xc 0x200(256),0x200 # partially clear lowcore |
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xc 0x300(256),0x300 |
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xc 0xe00(256),0xe00 |
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xc 0xf00(256),0xf00 |
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lctlg %c0,%c15,.Lctl-.LPG0(%r13) # load control registers |
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stcke __LC_BOOT_CLOCK |
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mvc __LC_LAST_UPDATE_CLOCK(8),__LC_BOOT_CLOCK+1 |
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spt 6f-.LPG0(%r13) |
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mvc __LC_LAST_UPDATE_TIMER(8),6f-.LPG0(%r13) |
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l %r15,.Lstack-.LPG0(%r13) |
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brasl %r14,verify_facilities |
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brasl %r14,startup_kernel |
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SYM_CODE_END(startup_normal) |
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.Lstack: |
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.long BOOT_STACK_OFFSET + BOOT_STACK_SIZE - STACK_FRAME_OVERHEAD |
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.align 8 |
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6: .long 0x7fffffff,0xffffffff |
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.Lext_new_psw: |
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.quad 0x0002000180000000,0x1b0 # disabled wait |
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.Lpgm_new_psw: |
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.quad 0x0000000180000000,startup_pgm_check_handler |
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.Lio_new_psw: |
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.quad 0x0002000180000000,0x1f0 # disabled wait |
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.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space |
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.quad 0 # cr1: primary space segment table |
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.quad .Lduct # cr2: dispatchable unit control table |
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.quad 0 # cr3: instruction authorization |
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.quad 0xffff # cr4: instruction authorization |
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.quad .Lduct # cr5: primary-aste origin |
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.quad 0 # cr6: I/O interrupts |
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.quad 0 # cr7: secondary space segment table |
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.quad 0x0000000000008000 # cr8: access registers translation |
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.quad 0 # cr9: tracing off |
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.quad 0 # cr10: tracing off |
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.quad 0 # cr11: tracing off |
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.quad 0 # cr12: tracing off |
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.quad 0 # cr13: home space segment table |
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.quad 0xc0000000 # cr14: machine check handling off |
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.quad .Llinkage_stack # cr15: linkage stack operations |
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.section .dma.data,"aw",@progbits |
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.Lduct: .long 0,.Laste,.Laste,0,.Lduald,0,0,0 |
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.long 0,0,0,0,0,0,0,0 |
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.Llinkage_stack: |
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.long 0,0,0x89000000,0,0,0,0x8a000000,0 |
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.align 64 |
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.Laste: .quad 0,0xffffffffffffffff,0,0,0,0,0,0 |
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.align 128 |
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.Lduald:.rept 8 |
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.long 0x80000000,0,0,0 # invalid access-list entries |
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.endr |
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.previous |
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#include "head_kdump.S" |
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# |
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# This program check is active immediately after kernel start |
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# and until early_pgm_check_handler is set in kernel/early.c |
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# It simply saves general/control registers and psw in |
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# the save area and does disabled wait with a faulty address. |
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# |
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SYM_CODE_START_LOCAL(startup_pgm_check_handler) |
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stmg %r8,%r15,__LC_SAVE_AREA_SYNC |
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la %r8,4095 |
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stctg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r8) |
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stmg %r0,%r7,__LC_GPREGS_SAVE_AREA-4095(%r8) |
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mvc __LC_GPREGS_SAVE_AREA-4095+64(64,%r8),__LC_SAVE_AREA_SYNC |
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mvc __LC_PSW_SAVE_AREA-4095(16,%r8),__LC_PGM_OLD_PSW |
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mvc __LC_RETURN_PSW(16),__LC_PGM_OLD_PSW |
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ni __LC_RETURN_PSW,0xfc # remove IO and EX bits |
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ni __LC_RETURN_PSW+1,0xfb # remove MCHK bit |
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oi __LC_RETURN_PSW+1,0x2 # set wait state bit |
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larl %r9,.Lold_psw_disabled_wait |
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stg %r9,__LC_PGM_NEW_PSW+8 |
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l %r15,.Ldump_info_stack-.Lold_psw_disabled_wait(%r9) |
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brasl %r14,print_pgm_check_info |
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.Lold_psw_disabled_wait: |
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la %r8,4095 |
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lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r8) |
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lpswe __LC_RETURN_PSW # disabled wait |
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SYM_CODE_END(startup_pgm_check_handler) |
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.Ldump_info_stack: |
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.long 0x5000 + PAGE_SIZE - STACK_FRAME_OVERHEAD |
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# |
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# params at 10400 (setup.h) |
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# Must be keept in sync with struct parmarea in setup.h |
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# |
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.org PARMAREA |
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.quad 0 # IPL_DEVICE |
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.quad 0 # INITRD_START |
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.quad 0 # INITRD_SIZE |
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.quad 0 # OLDMEM_BASE |
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.quad 0 # OLDMEM_SIZE |
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.quad kernel_version # points to kernel version string |
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.org COMMAND_LINE |
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.byte "root=/dev/ram0 ro" |
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.byte 0 |
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.org EARLY_SCCB_OFFSET |
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.fill 4096 |
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.org HEAD_END
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