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192 lines
5.2 KiB
192 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2017 SiFive |
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*/ |
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#include <linux/cpu.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <asm/cacheinfo.h> |
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static struct riscv_cacheinfo_ops *rv_cache_ops; |
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void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops) |
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{ |
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rv_cache_ops = ops; |
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} |
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EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops); |
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const struct attribute_group * |
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cache_get_priv_group(struct cacheinfo *this_leaf) |
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{ |
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if (rv_cache_ops && rv_cache_ops->get_priv_group) |
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return rv_cache_ops->get_priv_group(this_leaf); |
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return NULL; |
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} |
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static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type) |
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{ |
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/* |
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* Using raw_smp_processor_id() elides a preemptability check, but this |
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* is really indicative of a larger problem: the cacheinfo UABI assumes |
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* that cores have a homonogenous view of the cache hierarchy. That |
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* happens to be the case for the current set of RISC-V systems, but |
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* likely won't be true in general. Since there's no way to provide |
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* correct information for these systems via the current UABI we're |
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* just eliding the check for now. |
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*/ |
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(raw_smp_processor_id()); |
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struct cacheinfo *this_leaf; |
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int index; |
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for (index = 0; index < this_cpu_ci->num_leaves; index++) { |
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this_leaf = this_cpu_ci->info_list + index; |
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if (this_leaf->level == level && this_leaf->type == type) |
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return this_leaf; |
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} |
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return NULL; |
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} |
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uintptr_t get_cache_size(u32 level, enum cache_type type) |
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{ |
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struct cacheinfo *this_leaf = get_cacheinfo(level, type); |
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return this_leaf ? this_leaf->size : 0; |
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} |
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uintptr_t get_cache_geometry(u32 level, enum cache_type type) |
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{ |
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struct cacheinfo *this_leaf = get_cacheinfo(level, type); |
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return this_leaf ? (this_leaf->ways_of_associativity << 16 | |
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this_leaf->coherency_line_size) : |
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0; |
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} |
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static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type, |
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unsigned int level, unsigned int size, |
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unsigned int sets, unsigned int line_size) |
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{ |
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this_leaf->level = level; |
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this_leaf->type = type; |
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this_leaf->size = size; |
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this_leaf->number_of_sets = sets; |
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this_leaf->coherency_line_size = line_size; |
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/* |
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* If the cache is fully associative, there is no need to |
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* check the other properties. |
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*/ |
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if (sets == 1) |
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return; |
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/* |
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* Set the ways number for n-ways associative, make sure |
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* all properties are big than zero. |
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*/ |
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if (sets > 0 && size > 0 && line_size > 0) |
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this_leaf->ways_of_associativity = (size / sets) / line_size; |
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} |
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static void fill_cacheinfo(struct cacheinfo **this_leaf, |
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struct device_node *node, unsigned int level) |
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{ |
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unsigned int size, sets, line_size; |
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if (!of_property_read_u32(node, "cache-size", &size) && |
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!of_property_read_u32(node, "cache-block-size", &line_size) && |
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!of_property_read_u32(node, "cache-sets", &sets)) { |
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ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size); |
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} |
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if (!of_property_read_u32(node, "i-cache-size", &size) && |
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!of_property_read_u32(node, "i-cache-sets", &sets) && |
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!of_property_read_u32(node, "i-cache-block-size", &line_size)) { |
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ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size); |
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} |
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if (!of_property_read_u32(node, "d-cache-size", &size) && |
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!of_property_read_u32(node, "d-cache-sets", &sets) && |
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!of_property_read_u32(node, "d-cache-block-size", &line_size)) { |
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ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size); |
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} |
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} |
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static int __init_cache_level(unsigned int cpu) |
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{ |
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); |
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struct device_node *np = of_cpu_device_node_get(cpu); |
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struct device_node *prev = NULL; |
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int levels = 0, leaves = 0, level; |
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if (of_property_read_bool(np, "cache-size")) |
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++leaves; |
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if (of_property_read_bool(np, "i-cache-size")) |
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++leaves; |
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if (of_property_read_bool(np, "d-cache-size")) |
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++leaves; |
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if (leaves > 0) |
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levels = 1; |
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prev = np; |
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while ((np = of_find_next_cache_node(np))) { |
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of_node_put(prev); |
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prev = np; |
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if (!of_device_is_compatible(np, "cache")) |
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break; |
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if (of_property_read_u32(np, "cache-level", &level)) |
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break; |
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if (level <= levels) |
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break; |
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if (of_property_read_bool(np, "cache-size")) |
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++leaves; |
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if (of_property_read_bool(np, "i-cache-size")) |
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++leaves; |
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if (of_property_read_bool(np, "d-cache-size")) |
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++leaves; |
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levels = level; |
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} |
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of_node_put(np); |
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this_cpu_ci->num_levels = levels; |
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this_cpu_ci->num_leaves = leaves; |
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return 0; |
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} |
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static int __populate_cache_leaves(unsigned int cpu) |
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{ |
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); |
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struct cacheinfo *this_leaf = this_cpu_ci->info_list; |
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struct device_node *np = of_cpu_device_node_get(cpu); |
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struct device_node *prev = NULL; |
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int levels = 1, level = 1; |
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/* Level 1 caches in cpu node */ |
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fill_cacheinfo(&this_leaf, np, level); |
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/* Next level caches in cache nodes */ |
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prev = np; |
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while ((np = of_find_next_cache_node(np))) { |
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of_node_put(prev); |
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prev = np; |
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if (!of_device_is_compatible(np, "cache")) |
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break; |
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if (of_property_read_u32(np, "cache-level", &level)) |
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break; |
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if (level <= levels) |
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break; |
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fill_cacheinfo(&this_leaf, np, level); |
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levels = level; |
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} |
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of_node_put(np); |
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return 0; |
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} |
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DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level) |
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DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)
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