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557 lines
12 KiB
557 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* MPIC timer driver |
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* |
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* Author: Dongsheng Wang <[email protected]> |
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* Li Yang <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/errno.h> |
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#include <linux/mm.h> |
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#include <linux/interrupt.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/of_irq.h> |
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#include <linux/syscore_ops.h> |
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#include <sysdev/fsl_soc.h> |
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#include <asm/io.h> |
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#include <asm/mpic_timer.h> |
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#define FSL_GLOBAL_TIMER 0x1 |
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/* Clock Ratio |
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* Divide by 64 0x00000300 |
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* Divide by 32 0x00000200 |
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* Divide by 16 0x00000100 |
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* Divide by 8 0x00000000 (Hardware default div) |
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*/ |
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#define MPIC_TIMER_TCR_CLKDIV 0x00000300 |
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#define MPIC_TIMER_TCR_ROVR_OFFSET 24 |
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#define TIMER_STOP 0x80000000 |
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#define GTCCR_TOG 0x80000000 |
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#define TIMERS_PER_GROUP 4 |
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#define MAX_TICKS (~0U >> 1) |
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#define MAX_TICKS_CASCADE (~0U) |
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#define TIMER_OFFSET(num) (1 << (TIMERS_PER_GROUP - 1 - num)) |
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struct timer_regs { |
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u32 gtccr; |
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u32 res0[3]; |
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u32 gtbcr; |
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u32 res1[3]; |
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u32 gtvpr; |
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u32 res2[3]; |
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u32 gtdr; |
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u32 res3[3]; |
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}; |
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struct cascade_priv { |
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u32 tcr_value; /* TCR register: CASC & ROVR value */ |
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unsigned int cascade_map; /* cascade map */ |
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unsigned int timer_num; /* cascade control timer */ |
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}; |
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struct timer_group_priv { |
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struct timer_regs __iomem *regs; |
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struct mpic_timer timer[TIMERS_PER_GROUP]; |
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struct list_head node; |
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unsigned int timerfreq; |
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unsigned int idle; |
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unsigned int flags; |
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spinlock_t lock; |
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void __iomem *group_tcr; |
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}; |
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static struct cascade_priv cascade_timer[] = { |
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/* cascade timer 0 and 1 */ |
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{0x1, 0xc, 0x1}, |
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/* cascade timer 1 and 2 */ |
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{0x2, 0x6, 0x2}, |
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/* cascade timer 2 and 3 */ |
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{0x4, 0x3, 0x3} |
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}; |
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static LIST_HEAD(timer_group_list); |
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static void convert_ticks_to_time(struct timer_group_priv *priv, |
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const u64 ticks, time64_t *time) |
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{ |
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*time = (u64)div_u64(ticks, priv->timerfreq); |
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} |
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/* the time set by the user is converted to "ticks" */ |
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static int convert_time_to_ticks(struct timer_group_priv *priv, |
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time64_t time, u64 *ticks) |
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{ |
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u64 max_value; /* prevent u64 overflow */ |
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max_value = div_u64(ULLONG_MAX, priv->timerfreq); |
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if (time > max_value) |
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return -EINVAL; |
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*ticks = (u64)time * (u64)priv->timerfreq; |
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return 0; |
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} |
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/* detect whether there is a cascade timer available */ |
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static struct mpic_timer *detect_idle_cascade_timer( |
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struct timer_group_priv *priv) |
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{ |
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struct cascade_priv *casc_priv; |
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unsigned int map; |
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unsigned int array_size = ARRAY_SIZE(cascade_timer); |
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unsigned int num; |
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unsigned int i; |
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unsigned long flags; |
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casc_priv = cascade_timer; |
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for (i = 0; i < array_size; i++) { |
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spin_lock_irqsave(&priv->lock, flags); |
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map = casc_priv->cascade_map & priv->idle; |
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if (map == casc_priv->cascade_map) { |
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num = casc_priv->timer_num; |
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priv->timer[num].cascade_handle = casc_priv; |
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/* set timer busy */ |
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priv->idle &= ~casc_priv->cascade_map; |
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spin_unlock_irqrestore(&priv->lock, flags); |
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return &priv->timer[num]; |
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} |
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spin_unlock_irqrestore(&priv->lock, flags); |
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casc_priv++; |
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} |
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return NULL; |
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} |
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static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks, |
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unsigned int num) |
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{ |
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struct cascade_priv *casc_priv; |
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u32 tcr; |
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u32 tmp_ticks; |
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u32 rem_ticks; |
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/* set group tcr reg for cascade */ |
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casc_priv = priv->timer[num].cascade_handle; |
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if (!casc_priv) |
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return -EINVAL; |
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tcr = casc_priv->tcr_value | |
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(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET); |
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setbits32(priv->group_tcr, tcr); |
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tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks); |
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out_be32(&priv->regs[num].gtccr, 0); |
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out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP); |
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out_be32(&priv->regs[num - 1].gtccr, 0); |
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out_be32(&priv->regs[num - 1].gtbcr, rem_ticks); |
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return 0; |
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} |
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static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv, |
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u64 ticks) |
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{ |
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struct mpic_timer *allocated_timer; |
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/* Two cascade timers: Support the maximum time */ |
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const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE; |
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int ret; |
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if (ticks > max_ticks) |
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return NULL; |
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/* detect idle timer */ |
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allocated_timer = detect_idle_cascade_timer(priv); |
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if (!allocated_timer) |
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return NULL; |
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/* set ticks to timer */ |
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ret = set_cascade_timer(priv, ticks, allocated_timer->num); |
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if (ret < 0) |
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return NULL; |
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return allocated_timer; |
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} |
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static struct mpic_timer *get_timer(time64_t time) |
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{ |
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struct timer_group_priv *priv; |
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struct mpic_timer *timer; |
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u64 ticks; |
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unsigned int num; |
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unsigned int i; |
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unsigned long flags; |
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int ret; |
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list_for_each_entry(priv, &timer_group_list, node) { |
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ret = convert_time_to_ticks(priv, time, &ticks); |
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if (ret < 0) |
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return NULL; |
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if (ticks > MAX_TICKS) { |
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if (!(priv->flags & FSL_GLOBAL_TIMER)) |
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return NULL; |
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timer = get_cascade_timer(priv, ticks); |
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if (!timer) |
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continue; |
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return timer; |
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} |
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for (i = 0; i < TIMERS_PER_GROUP; i++) { |
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/* one timer: Reverse allocation */ |
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num = TIMERS_PER_GROUP - 1 - i; |
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spin_lock_irqsave(&priv->lock, flags); |
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if (priv->idle & (1 << i)) { |
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/* set timer busy */ |
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priv->idle &= ~(1 << i); |
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/* set ticks & stop timer */ |
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out_be32(&priv->regs[num].gtbcr, |
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ticks | TIMER_STOP); |
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out_be32(&priv->regs[num].gtccr, 0); |
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priv->timer[num].cascade_handle = NULL; |
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spin_unlock_irqrestore(&priv->lock, flags); |
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return &priv->timer[num]; |
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} |
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spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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} |
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return NULL; |
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} |
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/** |
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* mpic_start_timer - start hardware timer |
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* @handle: the timer to be started. |
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* |
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* It will do ->fn(->dev) callback from the hardware interrupt at |
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* the 'time64_t' point in the future. |
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*/ |
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void mpic_start_timer(struct mpic_timer *handle) |
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{ |
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struct timer_group_priv *priv = container_of(handle, |
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struct timer_group_priv, timer[handle->num]); |
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clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); |
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} |
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EXPORT_SYMBOL(mpic_start_timer); |
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/** |
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* mpic_stop_timer - stop hardware timer |
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* @handle: the timer to be stoped |
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* |
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* The timer periodically generates an interrupt. Unless user stops the timer. |
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*/ |
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void mpic_stop_timer(struct mpic_timer *handle) |
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{ |
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struct timer_group_priv *priv = container_of(handle, |
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struct timer_group_priv, timer[handle->num]); |
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struct cascade_priv *casc_priv; |
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setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP); |
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casc_priv = priv->timer[handle->num].cascade_handle; |
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if (casc_priv) { |
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out_be32(&priv->regs[handle->num].gtccr, 0); |
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out_be32(&priv->regs[handle->num - 1].gtccr, 0); |
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} else { |
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out_be32(&priv->regs[handle->num].gtccr, 0); |
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} |
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} |
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EXPORT_SYMBOL(mpic_stop_timer); |
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/** |
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* mpic_get_remain_time - get timer time |
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* @handle: the timer to be selected. |
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* @time: time for timer |
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* |
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* Query timer remaining time. |
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*/ |
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void mpic_get_remain_time(struct mpic_timer *handle, time64_t *time) |
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{ |
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struct timer_group_priv *priv = container_of(handle, |
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struct timer_group_priv, timer[handle->num]); |
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struct cascade_priv *casc_priv; |
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u64 ticks; |
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u32 tmp_ticks; |
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casc_priv = priv->timer[handle->num].cascade_handle; |
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if (casc_priv) { |
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tmp_ticks = in_be32(&priv->regs[handle->num].gtccr); |
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tmp_ticks &= ~GTCCR_TOG; |
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ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE; |
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tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr); |
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ticks += tmp_ticks; |
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} else { |
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ticks = in_be32(&priv->regs[handle->num].gtccr); |
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ticks &= ~GTCCR_TOG; |
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} |
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convert_ticks_to_time(priv, ticks, time); |
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} |
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EXPORT_SYMBOL(mpic_get_remain_time); |
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/** |
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* mpic_free_timer - free hardware timer |
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* @handle: the timer to be removed. |
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* |
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* Free the timer. |
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* |
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* Note: can not be used in interrupt context. |
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*/ |
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void mpic_free_timer(struct mpic_timer *handle) |
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{ |
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struct timer_group_priv *priv = container_of(handle, |
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struct timer_group_priv, timer[handle->num]); |
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struct cascade_priv *casc_priv; |
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unsigned long flags; |
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mpic_stop_timer(handle); |
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casc_priv = priv->timer[handle->num].cascade_handle; |
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free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev); |
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spin_lock_irqsave(&priv->lock, flags); |
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if (casc_priv) { |
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u32 tcr; |
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tcr = casc_priv->tcr_value | (casc_priv->tcr_value << |
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MPIC_TIMER_TCR_ROVR_OFFSET); |
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clrbits32(priv->group_tcr, tcr); |
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priv->idle |= casc_priv->cascade_map; |
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priv->timer[handle->num].cascade_handle = NULL; |
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} else { |
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priv->idle |= TIMER_OFFSET(handle->num); |
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} |
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spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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EXPORT_SYMBOL(mpic_free_timer); |
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/** |
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* mpic_request_timer - get a hardware timer |
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* @fn: interrupt handler function |
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* @dev: callback function of the data |
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* @time: time for timer |
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* |
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* This executes the "request_irq", returning NULL |
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* else "handle" on success. |
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*/ |
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struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev, |
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time64_t time) |
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{ |
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struct mpic_timer *allocated_timer; |
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int ret; |
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if (list_empty(&timer_group_list)) |
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return NULL; |
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if (time < 0) |
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return NULL; |
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allocated_timer = get_timer(time); |
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if (!allocated_timer) |
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return NULL; |
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ret = request_irq(allocated_timer->irq, fn, |
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IRQF_TRIGGER_LOW, "global-timer", dev); |
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if (ret) { |
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mpic_free_timer(allocated_timer); |
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return NULL; |
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} |
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allocated_timer->dev = dev; |
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return allocated_timer; |
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} |
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EXPORT_SYMBOL(mpic_request_timer); |
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static int timer_group_get_freq(struct device_node *np, |
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struct timer_group_priv *priv) |
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{ |
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u32 div; |
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if (priv->flags & FSL_GLOBAL_TIMER) { |
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struct device_node *dn; |
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dn = of_find_compatible_node(NULL, NULL, "fsl,mpic"); |
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if (dn) { |
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of_property_read_u32(dn, "clock-frequency", |
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&priv->timerfreq); |
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of_node_put(dn); |
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} |
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} |
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if (priv->timerfreq <= 0) |
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return -EINVAL; |
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if (priv->flags & FSL_GLOBAL_TIMER) { |
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div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8; |
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priv->timerfreq /= div; |
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} |
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return 0; |
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} |
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static int timer_group_get_irq(struct device_node *np, |
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struct timer_group_priv *priv) |
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{ |
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const u32 all_timer[] = { 0, TIMERS_PER_GROUP }; |
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const u32 *p; |
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u32 offset; |
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u32 count; |
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unsigned int i; |
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unsigned int j; |
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unsigned int irq_index = 0; |
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unsigned int irq; |
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int len; |
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p = of_get_property(np, "fsl,available-ranges", &len); |
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if (p && len % (2 * sizeof(u32)) != 0) { |
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pr_err("%pOF: malformed available-ranges property.\n", np); |
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return -EINVAL; |
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} |
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if (!p) { |
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p = all_timer; |
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len = sizeof(all_timer); |
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} |
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len /= 2 * sizeof(u32); |
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for (i = 0; i < len; i++) { |
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offset = p[i * 2]; |
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count = p[i * 2 + 1]; |
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for (j = 0; j < count; j++) { |
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irq = irq_of_parse_and_map(np, irq_index); |
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if (!irq) { |
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pr_err("%pOF: irq parse and map failed.\n", np); |
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return -EINVAL; |
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} |
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/* Set timer idle */ |
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priv->idle |= TIMER_OFFSET((offset + j)); |
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priv->timer[offset + j].irq = irq; |
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priv->timer[offset + j].num = offset + j; |
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irq_index++; |
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} |
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} |
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return 0; |
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} |
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static void timer_group_init(struct device_node *np) |
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{ |
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struct timer_group_priv *priv; |
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unsigned int i = 0; |
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int ret; |
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priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL); |
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if (!priv) { |
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pr_err("%pOF: cannot allocate memory for group.\n", np); |
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return; |
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} |
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if (of_device_is_compatible(np, "fsl,mpic-global-timer")) |
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priv->flags |= FSL_GLOBAL_TIMER; |
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priv->regs = of_iomap(np, i++); |
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if (!priv->regs) { |
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pr_err("%pOF: cannot ioremap timer register address.\n", np); |
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goto out; |
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} |
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if (priv->flags & FSL_GLOBAL_TIMER) { |
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priv->group_tcr = of_iomap(np, i++); |
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if (!priv->group_tcr) { |
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pr_err("%pOF: cannot ioremap tcr address.\n", np); |
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goto out; |
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} |
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} |
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ret = timer_group_get_freq(np, priv); |
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if (ret < 0) { |
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pr_err("%pOF: cannot get timer frequency.\n", np); |
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goto out; |
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} |
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ret = timer_group_get_irq(np, priv); |
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if (ret < 0) { |
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pr_err("%pOF: cannot get timer irqs.\n", np); |
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goto out; |
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} |
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spin_lock_init(&priv->lock); |
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/* Init FSL timer hardware */ |
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if (priv->flags & FSL_GLOBAL_TIMER) |
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setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); |
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list_add_tail(&priv->node, &timer_group_list); |
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return; |
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out: |
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if (priv->regs) |
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iounmap(priv->regs); |
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if (priv->group_tcr) |
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iounmap(priv->group_tcr); |
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kfree(priv); |
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} |
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static void mpic_timer_resume(void) |
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{ |
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struct timer_group_priv *priv; |
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list_for_each_entry(priv, &timer_group_list, node) { |
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/* Init FSL timer hardware */ |
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if (priv->flags & FSL_GLOBAL_TIMER) |
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setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV); |
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} |
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} |
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static const struct of_device_id mpic_timer_ids[] = { |
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{ .compatible = "fsl,mpic-global-timer", }, |
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{}, |
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}; |
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static struct syscore_ops mpic_timer_syscore_ops = { |
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.resume = mpic_timer_resume, |
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}; |
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static int __init mpic_timer_init(void) |
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{ |
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struct device_node *np = NULL; |
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for_each_matching_node(np, mpic_timer_ids) |
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timer_group_init(np); |
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register_syscore_ops(&mpic_timer_syscore_ops); |
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if (list_empty(&timer_group_list)) |
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return -ENODEV; |
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return 0; |
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} |
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subsys_initcall(mpic_timer_init);
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