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159 lines
5.9 KiB
159 lines
5.9 KiB
/* |
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* Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem |
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* ctlr/EPIC/etc. |
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* |
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* Author: Mark A. Greer |
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* [email protected] |
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* |
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under |
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* the terms of the GNU General Public License version 2. This program |
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* is licensed "as is" without any warranty of any kind, whether express |
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* or implied. |
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*/ |
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#ifndef __PPC_KERNEL_MPC10X_H |
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#define __PPC_KERNEL_MPC10X_H |
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#include <linux/pci_ids.h> |
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#include <asm/pci-bridge.h> |
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/* |
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* The values here don't completely map everything but should work in most |
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* cases. |
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* |
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* MAP A (PReP Map) |
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* Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff |
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* Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff |
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* PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 |
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* |
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* MAP B (CHRP Map) |
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* Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff |
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* Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff |
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* PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 |
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*/ |
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/* |
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* Define the vendor/device IDs for the various bridges--should be added to |
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* <linux/pci_ids.h> |
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*/ |
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#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
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PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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/* Define the type of map to use */ |
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#define MPC10X_MEM_MAP_A 1 |
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#define MPC10X_MEM_MAP_B 2 |
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/* Map A (PReP Map) Defines */ |
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#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 |
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#define MPC10X_MAPA_CNFG_DATA 0x80000cfc |
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#define MPC10X_MAPA_ISA_IO_BASE 0x80000000 |
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#define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 |
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#define MPC10X_MAPA_DRAM_OFFSET 0x80000000 |
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#define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0 |
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#define MPC10X_MAPA_PCI_IO_START 0x00000000 |
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#define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) |
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#define MPC10X_MAPA_PCI_MEM_START 0x00000000 |
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#define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) |
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#define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ |
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MPC10X_MAPA_PCI_MEM_START) |
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/* Map B (CHRP Map) Defines */ |
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#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 |
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#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
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#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 |
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#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 |
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#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 |
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#define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000 |
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#define MPC10X_MAPB_PCI_IO_START 0x00000000 |
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#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) |
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#define MPC10X_MAPB_PCI_MEM_START 0x80000000 |
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#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) |
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#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ |
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MPC10X_MAPB_PCI_MEM_START) |
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/* Miscellaneous Configuration register offsets */ |
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#define MPC10X_CFG_PIR_REG 0x09 |
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#define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 |
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#define MPC10X_CFG_PIR_AGENT 0x01 |
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#define MPC10X_CFG_EUMBBAR 0x78 |
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#define MPC10X_CFG_PICR1_REG 0xa8 |
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#define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 |
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#define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 |
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#define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 |
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#define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 |
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#define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 |
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#define MPC10X_CFG_PICR2_REG 0xac |
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#define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 |
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#define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 |
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#define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ |
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#define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ |
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#define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ |
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#define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ |
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#define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ |
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/* Define offsets for the memory controller registers in the config space */ |
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#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ |
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#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ |
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#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ |
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#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ |
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#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ |
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#define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ |
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#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ |
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#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ |
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#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 |
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/* Define some offset in the EUMB */ |
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#define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ |
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#define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ |
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#define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ |
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#define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ |
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#define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ |
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#define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ |
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#define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ |
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#define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ |
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#define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ |
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#define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ |
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#define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ |
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#define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ |
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#define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ |
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#define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ |
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#define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ |
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#define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ |
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#define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ |
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enum ppc_sys_devices { |
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MPC10X_IIC1, |
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MPC10X_DMA0, |
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MPC10X_DMA1, |
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MPC10X_UART0, |
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MPC10X_UART1, |
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NUM_PPC_SYS_DEVS, |
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}; |
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int mpc10x_bridge_init(struct pci_controller *hose, |
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uint current_map, |
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uint new_map, |
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uint phys_eumb_base); |
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unsigned long mpc10x_get_mem_size(uint mem_map); |
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int mpc10x_enable_store_gathering(struct pci_controller *hose); |
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int mpc10x_disable_store_gathering(struct pci_controller *hose); |
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/* For MPC107 boards that use the built-in openpic */ |
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void mpc10x_set_openpic(void); |
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#endif /* __PPC_KERNEL_MPC10X_H */
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